參數(shù)資料
型號: M12L128324A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類: DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 INCH, LEAD FREE, TSOP2-86
文件頁數(shù): 22/47頁
文件大?。?/td> 794K
代理商: M12L128324A-6TG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
22/47
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
5. Write Interrupted by Precharge & DQM
*Note : 1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt
but only another bank precharge of four banks operation.
CLK
i ) C M D
i i ) C M D
i i i ) C M D
i v) C M D
DQ M
DQ M
DQ M
DQ M
DQ
DQ
DQ
DQ
D1
D3
D1
D0
D2
D3
D0
D2
W R
(b) CL=3,BL= 4
R D
W R
R D
W R
D1
D3
D0
D2
D1
D3
D0
D2
R D
W R
H i - Z
D1
D3
D0
D2
Q0
*Not e 1
v) C M D
DQ M
DQ
R D
W R
H i - Z
R D
CLK
C M D
DQ M
DQ
D0
D1
D2
W R
* Not e 3
*Not e 2
Ma s k e d b y D Q M
D3
1) N o r m a l W r i t e ( B L = 4 )
t
RDL(min)
PRE
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