參數(shù)資料
型號(hào): M12L128324A-6TG
廠商: ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC
元件分類(lèi): DRAM
英文描述: 1M x 32 Bit x 4 Banks Synchronous DRAM
中文描述: 4M X 32 SYNCHRONOUS DRAM, 5.5 ns, PDSO86
封裝: 0.400 INCH, LEAD FREE, TSOP2-86
文件頁(yè)數(shù): 10/47頁(yè)
文件大小: 794K
代理商: M12L128324A-6TG
ES MT
M12L128324A
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2006
Revision
:
1.2
10/47
SIMPLIFIED TRUTH TABLE
COMMAND
CKEn-1
CKEn
CS RAS
CAS
WE
DQM BA0,1 A10/AP
A9~A0
Note
Register
Mode Register set
H
X
L
L
L
L
X
OP CODE
1,2
Auto Refresh
H
3
Entry
H
L
L
L
L
H
X
X
3
L
H
H
H
X
3
Refresh
Self
Refresh
Exit
L
H
H
X
X
X
X
X
3
Bank Active & Row Addr.
H
X
L
L
H
H
X
V
Row Address
Auto Precharge Disable
L
4
Read &
Column Address
Auto Precharge Enable
H
X
L
H
L
H
X
V
H
Column
Address
(A0~A7)
4,5
Auto Precharge Disable
L
4
Write &
Column Address
Auto Precharge Enable
H
X
L
H
L
L
X
V
H
Column
Address
(A0~A7)
4,5
Burst Stop
H
X
L
H
H
L
X
X
6
Bank Selection
V
L
Precharge
All Banks
H
X
L
L
H
L
X
X
H
X
H
X
X
X
Entry
H
L
L
V
V
V
X
Clock Suspend or
Active Power Down
Exit
L
H
X
X
X
X
X
X
H
X
X
X
Entry
H
L
L
H
H
H
X
H
X
X
X
Precharge Power Down Mode
Exit
L
H
L
V
V
V
X
X
DQM
H
X
V
X
7
H
X
X
X
No Operating Command
H
X
L
H
H
H
X
X
(V = Valid , X = Don’t Care. H = Logic High , L = Logic Low )
Note : 1.OP Code : Operating Code
A0~A11 & BA0~BA1 : Program keys. (@ MRS)
2.MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3.Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge of command is meant by “Auto”.
Auto/self refresh can be issued only at all banks idle state.
4.BA0~BA1 : Bank select addresses.
If both BA1 and BA0 are “Low” at read ,write , row active and precharge ,bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read ,write , row active and precharge ,bank B is selected.
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