參數(shù)資料
型號(hào)： LXT9860AHC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁數(shù)： 89/96頁
文件大?。?/td> 1309K
代理商： LXT9860AHC
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Datasheet
89
5.4.1
Repeater Configuration Register
This register contains many of the global repeater settings. The Repeater Configuration Register is
described in
Table 71
. Refer to
Table 70 on page 90
for bit assignments of the Repeater
Configuration Register.
Port LED Control Register
R/W
0B2
This register provides a measure of software control over the
port LEDs. Refer to
Table 74 on page 91
for bit assignments.
During reset, the state of this register is all 1s. If a manager is
present, this register remains in the all 1s state after reset.
Otherwise, the bits default to hardware control. Encoding is as
follows:
Bits 1 : 0
Modes 1 & 3
Mode 2
0 0
LED off
LED off
0 1
Reserved
LED fast blink
1 0
2
Hardware Control
Hardware Control
1 1
3
LED off
LED on steady
LED Timer Control Register
R/W
0B3
Refer to
Table 75 on page 91
for bit assignments. Bits 8-15 of
this register set the fast blink frequency of the LEDs. Bits 0-7 set
the slow blink frequency. The same formula is used in each case,
with a maximum of 128 Hz and a minimum of 0.5 Hz.
Example:
fast blink = x32 (0.4 sec)
slow blink = xCC (1.6 sec)
Repeater Reset Register
W
0B5
Writing any data value to this register with the Least Significant
Bit (LSB) = 1 causes the repeater functional logic to reset. (All
bits other than LSB do not matter.) The counters and
configuration information will be held static and will not be reset.
(default = 0s)
Software Reset Register
W
0B6
Writing any data value to this register with the Least Significant
Bit (LSB) = 1 is identical to a hardware reset. (All bits other than
LSB do not matter.) Everything is reset except the Source
Address RAM. (default = 0s)
Assign Address Register
(1 and 2)
W
188, 189
Refer to
Table 76 on page 91
for bit assignments. Writing a valid
48-bit ID (one that matches the EPROM ID) to this register
causes the device to change its Hub ID to the contents of the
EPROM ID register listed below. This register cannot be read.
EPROM Address Register
(1 and 2)
R
190, 191
These two registers contain the 48-bit ID read in from EPROM at
power-up. Refer to
Table 77 on page 91
for bit assignments.
Table 69. Configuration Registers (Continued)
Name
Type
1
Addr
Description
1. R = Read only; W = Write only; R/W = Read /Write.
2. Default value if manager is not present.
3. Default value if manager is present.
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