參數(shù)資料
型號： LXT9860AHC
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù)： 11/96頁
文件大?。?/td> 1309K
代理商： LXT9860AHC
LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Datasheet
11
Table 1. Mode Control Signal Descriptions
Pin
Symbol
Type
1
Description
189
188
PORT1_SPD0
PORT1_SPD1
TTL Input,
PU,
Latched on
reset
Speed Select - Ports 1 through 4.
These pins set the default value of the Port
Speed Control Register for the associated port as follows:
187
186
PORT2_SPD0
PORT2_SPD1
SPD1
0
0
1
1
SPD0
0
1
0
1
Mode
Allow 10/100 auto-negotiation/parallel detection.
Force 10BASE-T.
Force 100BASE-FX.
Force 100BASE-TX.
185
184
PORT3_SPD0
PORT3_SPD1
183
182
PORT4_SPD0
PORT4_SPD1
100
PORT5_SPD
TTL Input,
PU
Speed Select - Port 5.
Selects operating speed of the MII (MAC) interface. Also
selects the segment on which statistics are kept.
High = 100 Mbps. Low = 10 Mbps.
(Port 5 speed of 10 Mbps is available when PHY mode is selected.)
99
PORT5_SEL
TTL Input,
PU
Mode Select - Port 5.
Selects operating mode of the MII interface. Pin is
monitored at power-up and reset. Subsequent changes have no effect.
High = PHY Mode (LXT980 acts as PHY side of the MII.)
Low = MAC Mode (LXT980 acts as MAC side of the MII.)
197
196
195
194
193
192
191
190
CONFIG0
CONFIG1
CONFIG2
CONFIG3
CONFIG4
CONFIG5
CONFIG6
CONFIG7
TTL Input,
PD
Configuration Register Inputs.
These inputs allow the user to store system-
specific information (board type, plug-in cards, status, etc.) in the Serial
Configuration Register (address AC). This register may be read remotely through
the Serial Management Interface (SMI).
1. NC = No Clamp. Pad will not clamp input in the absence of power.
PU = Input contains pull-up.
PD = Input contains pull-down.
TTL = Transistor-Transistor Logic.
Table 2. PHY Mode MII Interface Signal Descriptions
Pin
Symbol
Type
1
Description
29
30
32
33
MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3
Output
TTL
Receive Data.
The LXT980 transmits received data to the controller on these outputs. Data
is driven on the falling edge of MII_RXCLK.
26
MII_RXDV
Output
TTL
Receive Data Valid.
Active High signal, synchronous to MII_RXCLK, indicates valid data
on MII_RXD<3:0>.
25
MII_RXCLK
Output
TTL
Receive Clock.
MII receive clock for expansion port. This is a 2.5 or 25 MHz clock derived
from the CLK25 input (refer to
Table 11
).
24
MII_RXER
Output
TTL
Receive Error.
Active High signal, synchronous to MII_RXCLK, indicates invalid data on
MII_RXD<3:0>.
22
MII_TXER
Input
TTL
Transmit Error.
MII_TXER is a 100M-only signal. The MAC asserts this input when an
error has occurred in the transmit data stream. The LXT980 responds by sending
‘
Invalid
Code Symbols
’
on the line.
1. MII interface pins reverse direction based on PHY/MAC mode. Direction listed is for PHY mode.
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