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參數(shù)資料
| 型號： | LXT980QC |
| 英文描述： | LAN HUB CONTROLLER |
| 中文描述： | 局域網(wǎng)集線器控制器 |
| 文件頁數(shù)： | 79/96頁 |
| 文件大小： | 1309K |
| 代理商： | LXT980QC |
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LXT980/980A Dual-Speed, 5-Port Fast Ethernet Repeater
Datasheet
79
5.0
Register Definitions
The LXT980/980A register set is composed of multiple 32-bit registers of the types listed in
Table
49
. All register addresses are hexadecimal.
5.1
Counter Registers
Table 50
shows bit assignments. When reading a 64-bit counter, read the lower address (lower 32
bits of counter) first, followed by the upper address. The first read causes all 64 bits to be
simultaneously latched into an internal holding register. The second read is directed to this holding
register. The statistics bit must be set off to write to the counters.
5.1.1
Port Counter Registers
The Port Counter descriptions in
Table 51
are intended to be illustrative. For the exact definition of
these counters, refer to the Repeater MIB, RFC 1516. All counters count packets, octets or events
that were received at each port. In the descriptions, the length of a packet never includes preamble
or framing bits (start of frame, end of frame, dribble bits, etc.), but an
“
event
”
does include these
items.
Table 49. Register Set
Base
Address
1
Register Type
Bit Assignments & Description
00X
Port 1 Counters (TP/FX)
Refer to
Table 50
and
Table 51
.
01X
Port 2 Counters (TP/FX)
02X
Port 3 Counters (TP/FX)
03X
Port 4 Counters (TP/FX)
04X
Port 5 Counters (MII)
05X
Additional Counters (100 only)
05X, 06X
RMON Counters
Refer to
Table 50
and
Table 52
.
07X
Port Addresses
Refer to
Table 53
and
Table 54
.
08X
Authorized Addresses
Refer to
Table 53
.
08X, 09X
Global Addresses
Refer to
Table 53
and
Table 55
.
09X
Port Control & Status
Refer to
Table 56 through Table 63
.
09X, 0AX, 0BX,
188, 189, 190,
191
General Setup/Status
Refer to
Table 64
through
Table 82
.
1. X = Offset address of register desired. Note that base register addresses for port counters are offset by 1 (00x refers to Port 1,
01X to Port 2, 02X to Port 3, 03X to Port 4 and 04X to Port 5).
Table 50. Counter Register Bit Assignments
31
30
29
28
27
26
25: 7
6
5
4
3
2
1
0
D31
D30
D29
D28
D27
D26
D25:D7
D6
D5
D4
D3
D2
D1
D0
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