參數(shù)資料
型號(hào)： LXT9762HC
英文描述： LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC
中文描述： 網(wǎng)絡(luò)收發(fā)器|六角| QFP封裝| 208PIN |塑料
文件頁數(shù)： 49/68頁
文件大?。?/td> 1177K
代理商： LXT9762HC
Low-Power Octal PHY
—
LXT9784
Datasheet
49
3.3.1
RMII Clock
In RMII mode of operation, the master input clock (MCLK) frequency should be 50 MHz ± 50
ppm, with a duty-cycle between 35% and 65% inclusive.
3.4
SMII Applications
The SMII ports provide eight low pin-count interfaces between the LXT9784
’
s eight PHYs and an
ASIC switch, as an alternative to the RMII interface. The SMII interface is composed of two
signals per port, a global synchronization signal, and a global reference clock.
Figure 13. Typical RMII Application
LXT9784
P0_MDI
P1_MDI
P2_MDI
P3_MDI
P4_MDI
P5_MDI
P6_MDI
P7_MDI
MDI Ports
RBIAS100_0
RBIAS10_0
Analog pins
LED0_[A:C]
LED1_[A:C]
LED2_[A:C]
LED3_[A:C]
LED4_[A:C]
LED5_[A:C]
LED6_[A:C]
LED7_[A:C]
Per Port
LEDs
MODE[2:0]
RESET
MCLK
FRC34
Configuration
MDIO
MDC
MII Management
Interface
ID[1:0]
PHY ID
RMII0_[6:0]
RMII1_[6:0]
RMII2_[6:0]
RMII3_[6:0]
RMII4_[6:0]
RMII5_[6:0]
RMII6_[6:0]
RMII7_[6:0]
RMII
Interfaces
TPIP
INT
Interrupt
RBIAS100_1
RBIAS10_1
SCRMBP
MDIX
BP4B5B
FRCLNK
SYNC
TCK
TI
TEXEC
TOUT
Test Port
TPIN
TPOP
TPON
RXD[1:0]
TXD[1:0]
CRSDV
TXEN
RXER
相關(guān)PDF資料
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