參數(shù)資料
型號： LXT9762HC
英文描述： LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC
中文描述： 網(wǎng)絡(luò)收發(fā)器|六角| QFP封裝| 208PIN |塑料
文件頁數(shù)： 3/68頁
文件大小： 1177K
代理商： LXT9762HC
Datasheet
3
Low-Power Octal PHY — LXT9784
Contents
1.0
2.0
Pin Assignments and Signal Descriptions
....................................................10
Functional Description
...........................................................................................29
2.1
Introduction..........................................................................................................29
2.2
LXT9784 Configuration .......................................................................................29
2.3
100BASE-TX Mode.............................................................................................30
2.3.1
100BASE-TX Receiver...........................................................................30
2.3.1.1 Digital Adaptive Equalizer .........................................................30
2.3.1.2 Receive Clock and Data Recovery............................................30
2.3.1.3 Baseline Wander Correction .....................................................31
2.3.1.4 Decoder.....................................................................................31
2.3.1.5 100BASE-TX Receive Framing.................................................31
2.3.1.6 100BASE-TX RMII Data Reception...........................................31
2.3.1.7 100BASE-TX SMII Data Reception...........................................31
2.3.1.8 100BASE-TX Receive Error Detection and Reporting ..............32
2.3.2
100BASE-TX Transmitter.......................................................................33
2.3.2.1 100BASE-TX 4B/5B Encoder....................................................33
2.3.2.2 100BASE-TX Scrambler and MLT-3 Encoder...........................33
2.3.2.3 Transmit Driver..........................................................................35
2.3.2.4 100BASE-TX Transmit Framing................................................35
2.4
10BASE-T Mode .................................................................................................36
2.4.1
10BASE-T Receiver...............................................................................36
2.4.1.1 10BASE-T Manchester Decoder...............................................36
2.4.1.2 10BASE-T Receive Buffer and Filter.........................................37
2.4.1.3 10BASE-T Error Detection and Reporting.................................37
2.4.1.4 10BASE-T Link Integrity............................................................37
2.4.1.5 10BASE-T Jabber Control Function..........................................37
2.4.1.6 10BASE-T Full Duplex ..............................................................38
2.4.2
10BASE-T Transmit ...............................................................................38
2.4.2.1 10BASE-T Manchester Encoder ...............................................38
2.4.2.2 10BASE-T Driver and Filter.......................................................38
2.5
MDI/MDI-X Function............................................................................................38
2.5.1
MDI/MDI-X Auto Switching Activation ....................................................39
2.5.2
MDI/MDI-X Algorithm .............................................................................39
2.6
Hardware Control Interface.................................................................................40
2.6.1
MDI-X (MDI Crossover)..........................................................................40
2.6.2
FRCLNK (Force Link).............................................................................40
2.6.3
FRC34 (Force 34 Transmit Pattern).......................................................40
2.6.4
BP4B5B (4B/5B Bypass)........................................................................40
2.6.5
SCRMBP (Scrambler Bypass) ...............................................................41
2.7
PHY Addresses...................................................................................................41
2.8
Link Status Interrupt............................................................................................41
2.9
Reset...................................................................................................................42
2.10
LED Operation.....................................................................................................42
2.11
MII Management Interface Operation..................................................................43
2.12
Test Port Operation.............................................................................................44
2.12.1 NAND-Tree Test.....................................................................................44
2.12.2 XNOR-Tree Test ....................................................................................45
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