參數(shù)資料
型號： LXT9762HC
英文描述： LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC
中文描述： 網(wǎng)絡收發(fā)器|六角| QFP封裝| 208PIN |塑料
文件頁數(shù)： 43/68頁
文件大?。?/td> 1177K
代理商： LXT9762HC
Low-Power Octal PHY
—
LXT9784
Datasheet
43
During reset, all LED drivers are active for approximately 2 seconds, then turned off.
2.11
MII Management Interface Operation
The LXT9784 provides PHY status and accepts PHY management information via the MII
management interface. This is accomplished via read and write operations to various registers
according to the IEEE802.3u Standard. A read or write of a particular register is called a
management frame, which is sent serially over the MDIO pin synchronous to MDC at a maximum
rate of 3 MHz. Read and write cycles are from the perspective of the controller. Therefore, the
controller would always drive the Start, Opcode, PHY Address and Register Address on to the
MDIO pin. For a write, the controller would also drive the transition bits and data. For a read, the
LXT9784 drives the transition bits and data onto the MDIO pin. The controller should drive
address and data on the falling edge of MDC and the LXT9784 latches that data on the rising edge
of MDC. The PHY addresses in the LXT9784 can be configured from 0-31. The management
frame structure is shown in
Table 19
.
This structure allows a controller or other management hardware, to query a PHY for status of the
link, auto-negotiation registers, or configure the PHY to one of many modes.
Table 20
defines the
protocol terms.
When MDIO and MDC are not in use, they should be connected to pull-up devices.
Table 17. LED Functionality
LED driver
Function
Description
LED
n
_A
link
solid
/activity
blink
With a good link the output is low, the output toggles at a rate
related to the utilization.
Refer to
Table 18
for the actual numbers.
LED
n
_B
speed
The output is low for 100 Mbps, high for 10 Mbps
LED
n
_C
collision
The output blinks low with collisions stretch rate of 10 ms.
1.
n
indicates Port Number.
Table 18. Activity LED Blink Rates
Percent Utilization
Blink Rate
1
Frequency
0-5%
slow
3 Hz
5-30%
medium
5 Hz
+30%
fast
7 Hz
1. Note: Duty Cycle = 50%
Table 19. MII Management Frame Format
Function
Preamble
Start
Frame
Opcode
PHY Adr
Reg adr
Turnaround
Data
Idle
READ
1...1
10
10
AAAAA
RRRRR
Z0
D[15:0]
Z
WRITE
1...1
01
01
AAAAA
RRRRR
10
D[15:0]
Z
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