參數(shù)資料
型號(hào)： LXT381BE
廠商： INTEL CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： Octal E1 Line Interface Unit
中文描述： DATACOM, PCM TRANSCEIVER, PBGA160
封裝： PLASTIC, BGA-160
文件頁(yè)數(shù)： 7/36頁(yè)
文件大?。?/td> 218K
代理商： LXT381BE
Octal E1 Line Interface
—
LXT381
Datasheet
7
Table 1. LXT381 Pin Description
Pin #
LQFP
Pin #
PBGA
Symbol
I/O
1
Description
1
B2
TPOS7
DI
Transmit Positive Data Input.
2
B1
TCLK7
DI
Transmit Clock Input.
When TCLK is active, TPOS and TNEG work as NRZ inputs. TPOS and
TNEG are sampled on the falling edge of TCLK.
If TCLK is held High, TPOS and TNEG work as RZ inputs. In this mode,
pulse widths are determined by TPOS and TNEG duty cycles. An analog
timer is used to determine if TCLK is high for at least 12
μ
seconds in order
to enable the above function.
If TCLK is held Low, the output drivers enter a low power high Z mode.
TCLK
Operating Mode
Clocked NRZ
H
RZ
L
Driver Tri-State
3
E3
ALOS6
DO
Analog Loss of Signal Output.
Please refer to the ALOS functional
description.
4
5
C3
C2
RNEG6
RPOS6
DO
DO
Receive Negative Data Output.
Receive Positive Data Output.
These pins act as RZ data receiver outputs. The output polarity is
selectable with RPOL The pins will be active High polarity when RPOL is
High and Active Low Polarity when RPOL is Low.
RPOS and RNEG will be active when the corresponding transceiver is in
LOS.
RPOS and RNEG will be in high impedance state if the RPD pin is Low.
6
C1
RCLK6
DO
Receive Clock Output.
RPOS and RNEG are internally connected to an
EXOR that is fed to the RCLK output for external clock recovery
applications. RCLK will be in high impedance state if the RPD pin is Low.
7
8
D3
D2
TNEG6
TPOS6
DI
DI
Transmit Negative Data Input.
Transmit Positive Data Input.
When TCLK is active, TPOS/TNEG are active high NRZ inputs. TPOS
indicates the transmission of a positive pulse whereas TNEG indicates the
transmission of a negative pulse. TPOS and TNEG are sampled on the
falling edge of TCLK.
If TCLK is held High, TPOS and TNEG work as RZ inputs. In this mode,
pulse widths are determined by TPOS and TNEG duty cycles. An analog
timer is used to determine if TCLK is high for at least 12
μ
seconds in order
to enable the above function.
TCLK
TPOS/TNEG Operating Mode
Clocked NRZ
H
RZ
9
D1
TCLK6
DI
Transmit Clock Input.
10
E1
RPD
DI
Receiver Power Down Input.
If RPD is Low, the complete receive path is
powered down and the output pins RCLK, RPOS and RNEG are switched
to Tri-state mode.
11
E2
GND
S
Ground.
This pin must be connected to Ground.
12
F1
GND
S
Ground.
This pin must be connected to Ground.
13
F2
GND
S
Ground.
This pin must be connected to Ground.
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not
Connected.
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