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參數(shù)資料
| 型號： | LXT381BE |
| 廠商： | INTEL CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | Octal E1 Line Interface Unit |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA160 |
| 封裝： | PLASTIC, BGA-160 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LXT381BE |
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LXT381
—
Octal E1 Line Interface
10
Datasheet
78
M14
RCLK2
DO
Receive Clock Output.
79
80
L12
L13
TNEG2
TPOS2
DI
DI
Transmit Negative Data Input.
Transmit Positive Data Input.
81
L14
TCLK2
DI
Transmit Clock Input.
82
K13
NC
NC
Not Connected.
This pin must be left open for normal operation.
83
K14
NC
NC
Not Connected.
This pin must be left open for normal operation.
84
J11
GND
S
Ground.
This pin must be connected to Ground.
85
J12
GND
S
Ground.
This pin must be connected to Ground.
86
J13
GND
S
Ground.
This pin must be connected to Ground.
87
J14
GND
S
Ground.
This pin must be connected to Ground.
88
H12
GND
S
Ground.
This pin must be connected to Ground.
89
H11
GND1
S
Ground (Core).
90
H14
VCC1
S
Power (Core).
91
G11
GNDIO1
S
Ground (I/O).
92
G14
VCCIO1
S
Power (I/O).
93
G13
AT2
AO
JTAG Analog Output Test Port 2.
94
H13
AT1
AI
JTAG Analog Input Test Port 1.
95
G12
TRST
DI
JTAG Controller Reset Input.
Input is used to reset JTAG controller.
TRST is pulled up internally and may be left disconnected.
96
F11
TMS
DI
JTAG Test Mode Select Input.
Used to control the test logic state
machine. Sampled on rising edge of TCK. TMS is pulled up internally and
may be left disconnected.
97
F14
TCK
DI
JTAG Clock Input.
Clock input for JTAG. Connect to GND when not used.
98
F13
TDO
DO
JTAG Data Output.
Test Data Output for JTAG. Used for reading all serial
configuration and test data from internal test logic. Updated on falling edge
of TCK.
99
F12
TDI
DI
JTAG Data Input.
Test Data input for JTAG. Used for loading serial
instructions and data into internal test logic. Sampled on rising edge of
TCK. TDI is pulled up internally and may be left disconnected.
100
D14
TCLK5
DI
Transmit Clock Input.
101
102
D13
D12
TPOS5
TNEG5
DI
DI
Transmit Positive Data Input.
Transmit Negative Data Input.
103
C14
RCLK5
DO
Receive Clock Output.
104
105
C13
C12
RPOS5
RNEG5
DO
DO
Receive Positive Data Output.
Receive Negative Data Output.
106
E12
ALOS5
DO
Analog Loss of Signal Output.
107
B14
TCLK4
DI
Transmit Clock Input.
Table 1. LXT381 Pin Description (Continued)
Pin #
LQFP
Pin #
PBGA
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not
Connected.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT381LE | Octal E1 Line Interface Unit |
| LXT381 | Octal E1 Line Interface Unit |
| LXT386 | QUAD T1/E1/J1 Transceiver |
| LXT400 | All Rate Extended Range Switched 56/DDS Transceiver |
| LXT441 | Switched 56/DDS Integrated DSU/CSU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT381LE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Octal E1 Line Interface Unit |
| LXT384/LXT386/LXT388 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LXT384/LXT386/LXT388 - LXT384/6/8 Twisted Pair Interface Without Component Changes |
| LXT384BE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT384LE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecomm/Datacomm |
| LXT386 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:QUAD T1/E1/J1 Transceiver |
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