參數(shù)資料
型號(hào)： LXT362PE
英文描述： PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
中文描述： 的PCM收發(fā)器|單|的T 1（DS1的）|的CMOS | LDCC | 28腳|塑料
文件頁(yè)數(shù)： 30/52頁(yè)
文件大?。?/td> 1187K
代理商： LXT362PE
LXT361
—
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
30
Datasheet
Table 13. Performance Status Register
Read Only, Address (A7-A0) = x010101x
Bit
Name
Function
0
LOS
1 = Loss of Signal occurred.
0 = Loss of Signal did not occur.
1
NLOOP
1 = Network loopback active.
0 = Network loopback not active.
2
AIS
1 = Alarm Indicator Signal detected.
0 = Alarm Indicator Signal not detected.
3
QRSS
1 = Quasi-Random Signal Source pattern detected.
0 = Quasi-Random Signal Source pattern not detected.
4
-
reserved
–
ignore.
5
DFMO
1 = Driver Failure Monitor Open detected.
0 = Driver Failure Monitor Open not detected.
6
BIST
1 = Built-In Self Test passed.
0 = Built-In Self Test did not pass (or was not run).
7
-
reserved
–
ignore.
Table 14. Equalizer Status Register
Read Only, Address (A7-A0) = x010110x
Bit
Name
Function
0
-
reserved
–
ignore (Least Significant Bit)
1
-
reserved
–
ignore
2
-
reserved
–
ignore
3
-
reserved
–
ignore
4
LATN4
Receive Line Attenuation Indicators. Convert this binary output to a decimal number and multiply
by 2.9 dB to determine the approximate cable attenuation as seen by the receiver.
For example, if LATN7-4 = 1010
(= 10
), then the receiver is seeing a signal attenuated by
approximately 29 dB (2.9 dB
x
10) of cable. This approximation assumes that a 3 V pulse was
transmitted.
5
LATN5
6
LATN6
7
LATN7
Table 15. Control Register #4
Read/Write,
Address (A7-A0) = x010111x
Bit
Name
Function
0
CODEV
1 = Enable detection of HDB3 code violations at the BPV pin along with bipolar violations and Zero
Substitution Violations (if enabled).
0 = Disable detection of HDB3 code violations
1
ZEROV
1 = Enable detection of HDB3 Zero Substitution Violations (four consecutive zeros). Note that Zero
Substitution Violations are reported at the BPV pin.
0 = Disable detection of HDB3 Zero Substitution Violations.
2
LOS2048
1 = Set LOS detection threshold to 2048 consecutive zeros.
0 = Set LOS detection threshold to 32 consecutive zeros (for E1 operation) or to 175 consecutive
zeros (for T1 operation).
3
COL32CM
1 = Set LOS clear condition criterion to receipt of 32 consecutive marks (E1 operation).
0 = Set LOS clear condition criterion to 12.5% mark density (E1 operation).
相關(guān)PDF資料
PDF描述
LXT362QE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT363LE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT363PE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
LXT363QE PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LXT362QE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT363LE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT363PE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC
LXT363QE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC
LXT36X/35X 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LXT36x/35x - LXT36x/35x Master Clock Requirements
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