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| 型號(hào)： | LXT362PE |
| 英文描述： | PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|LDCC|28PIN|PLASTIC |
| 中文描述： | 的PCM收發(fā)器|單|的T 1（DS1的）|的CMOS | LDCC | 28腳|塑料 |
| 文件頁(yè)數(shù)： | 29/52頁(yè) |
| 文件大?。?/td> | 1187K |
| 代理商： | LXT362PE |
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Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
—
LXT361
Datasheet
29
Table 11. Interrupt Clear Register
Read/Write, Address (A7-A0) = x010011x
Bit
Name
Function
1
0
CLOS
1 = Clear/Mask Loss of Signal interrupt.
0 = Enable Loss of Signal interrupt.
1
CNLOOP
1 = Clear/Mask Network loopback interrupt.
0 = Enable Network loopback interrupt.
2
CAIS
1 = Clear/Mask Alarm Indication Signal interrupt.
0 = Enable Alarm Indication Signal interrupt.
3
CQRSS
1 = Clear/Mask Quasi-Random Signal Source interrupt.
0 = Enable Quasi-Random Signal Source interrupt.
4
-
reserved
–
set to 1 for normal operation.
5
CDFMO
1 = Clear/Mask Driver Failure Monitor Open interrupt.
0 = Enable Driver Failure Monitor Open interrupt.
6
CESO
1 = Clear/Mask Elastic Store Overflow interrupt.
0 = Enable Elastic Store Overflow interrupt.
7
CESU
1 = Clear/Mask Elastic Store Underflow interrupt.
0 = Enable Elastic Store Underflow interrupt.
1. Leaving a 1 of in any of these bits masks the associated interrupt.
Table 12. Transition Status Register
Read Only, Address (A7-A0) = x010100x
Bit
Name
Function
0
TLOS
1 = Loss of Signal (LOS) has changed since last clear LOS interrupt occurred.
0 = No change in status.
1
TNLOOP
1 = NLOOP has changed since last clear NLOOP interrupt occurred.
0 = No change in status.
2
TAIS
1 = AIS has changed since last clear AIS interrupt occurred.
0 = No change in status.
3
TQRSS
1 = QRSS has changed since last clear QRSS interrupt occurred
1
.
0 = No change in status.
4
-
reserved-ignore.
5
TDFMO
1 = DFMO has changed since last clear DFMS interrupt occurred.
0 = No change in status.
6
ESOVR
1 = ES overflow status sticky bit
2
.
0 = No change in status.
7
ESUNF
1 = ES underflow status sticky bit
2
.
0 = No change in status.
1. A QRSS transition indicates receive QRSS pattern sync or loss. A simple error in QRSS pattern is not reported as a
transition.
2. Tripping the overflow or underflow indicator in the ES sets the ESOVR/ESUNF status bit(s). Reading the Transition Status
Register clears these bits. Setting CESO and CESU in the Interrupt Clear Register masks these interrupts.
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| LXT362QE | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC |
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