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參數(shù)資料
| 型號： | LU5X34F |
| 廠商： | Lineage Power |
| 英文描述： | Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器) |
| 中文描述： | 四個(gè)千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)四收發(fā)器） |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 445K |
| 代理商： | LU5X34F |
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Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Functional Description
The LU5X34F transceiver provides for data transmis-
sion over fiber or coaxial media at 1.0 Gbits/s to
1.25 Gbits/s. The block diagram of the quad transceiver
is shown in Figure 1 and the four-channel application
pinout for the 217-pin PBGA package is given in
Figure 3 and Table 3.
Transmitter Section
The transmitter accepts 8b/10b encoded bits in 10-bit
parallel form and converts to serial format for up to
1.25 Gbits/s transmission. The serial nonreturn to zero
(NRZ) bits are then shifted out of the device at a maxi-
mum rate of 1.25 Gbits/s. Internally, the device uses
two parallel shift registers that operate at half rate (i.e.,
a maximum of 625 MHz) for reduced power consump-
tion. The two shift registers drive the PECL output
buffer in an interleaved manner to construct the
1.25 Gbits/s output data stream.
The typical transmit-and-receive, high-speed I/O inter-
facing for a single-channel backplane application is
shown in Figure 9.
The transmit shift register and other circuits are driven
with clocks generated from a 500 MHz—625 MHz inter-
nal clock. This internal clock is sourced from a voltage-
controlled oscillator (VCO) that is locked to the external
reference of 100 MHz—125 MHz. The internal transmit
phase- lock loop multiplies the frequency of the input
reference clock by a factor of 5, and controls the trans-
mit jitter bandwidth with appropriate design of the jitter
transfer function. The transmit phase-lock loop gener-
ates multiple clock phases that are all used by each of
the four receiver circuits. The clock phases are derived
from the transmit VCO.
Receiver Section
Each of the quad receiver circuits recovers clock from
and retimes the serial input data. The data is input to
the receiver on differential PECL buffers. External ter-
mination resistors are supplied by the user in accor-
dance with ANSI standard, X3T11. The serial
differential inputs, HDINP and HDINN, are ac-coupled
to the device and internally biased to the PECL input
common-mode range center. See Figure 9 for the typi-
cal application and termination of the transmission
lines.
The receiver data-retiming circuit uses a digital timing
recovery loop that compares the phase of the input
data to multiple phases of the on-device VCO in the
transmit section. One of the phases is chosen to retime
the receive data. A digital low-pass filter is used in the
timing recovery loop to reject jitter from the data input.
A novel phase interpolation circuit permits the retiming
clock’s phase to be stepped with fine resolution for pre-
cise alignment of the sampling clock within the data
eye. Use of this digital data locking scheme for each
receiver advantageously avoids the use of multiple
analog phase-lock loops on-device that can potentially
injection lock to one another. Additionally, the digital
data locking loop maintains precise loop dynamics,
hence, the jitter transfer function is process and tem-
perature independent.
Lock to Reference
The receive circuit has two modes of operation: lock to
reference, and lock to data with retiming. When no data
or invalid data is present on the HDINP and HDINN
input pins, the user can program the device to ignore
the input data by setting LCKREFN equal to logic 0. In
this mode, neither the PECL input buffer nor the RX
parallel data bus toggles. In normal operation, the
LCKREFN is a logic 1 and the receiver attempts to lock
to the incoming data. If the input data is invalid or out-
side the nominal ± frequency range, the receive digital
PLL will simply ramp the phase of the output clock until
it locks to data.
Table 1. Receive Circuit Operating Modes
*
* REFCLK requirements are given in Table 4, and receive PLL specifications are given in Table 5.
Mode
Lock to Reference
Not applicable.
Lock to Receive Data
Continually attempts to lock to
data.
Not applicable.
LCKREFN = 1 (normal operation)
LCKREFN = 0
Lock to clock, output data does not
toggle. Disable PECL input buffer.
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