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參數(shù)資料
| 型號(hào)： | LU5X34F |
| 廠商： | Lineage Power |
| 英文描述： | Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器) |
| 中文描述： | 四個(gè)千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)四收發(fā)器） |
| 文件頁數(shù)： | 13/26頁 |
| 文件大?。?/td> | 445K |
| 代理商： | LU5X34F |
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13
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Input/Output Information
(continued)
Table 3e. Pinout—Common I/O
* For related information, see Table 18, Test Modes.
Table 3f. Pinout—Power I/O
Name
Pin
K16
I/O
Input/
Output
Input/
Output
Input
Level
Analog
Description
OLREF
PECL Level Set Resistor Terminal 1.
OLRVS
K17
Analog
PECL Level Set Resistor Terminal 2.
LPWR
J3
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL or
TTL/
CMOS
Device Low-Power Mode.
RESETN
G2
Input
Device Reset (Active-Low).
TEST5*
J2
Input/
Output
Input
Global Test Control Input/Output.
TEST4*
H1
Local Test Control Input.
TEST3*
H2
Input
Local Test Control Input.
TEST2*
G1
Input
Local Test Control Input.
TEST1*
H3
Input
Local Test Control Input.
BYPPLL
J1
Input
Test Control, PLL Bypass Mode.
REFCLK,
REFCLKN
K1, K2
Input
Reference Clock Input (100 MHz—125 MHz).
Used by the transmitter PLL to generate the
1.0 Gbits/s— 1.25 Gbits/s serial data; has a +100 ppm
tolerance requirement.
Name
V
DD
V
DD
P
V
DD
T
X
V
DD
R
V
SS
Pin
Description
D5, D8, D10, B13, H4, K4, P8, P10
G17, H16
D16, D17, F17, G16, L15, N16, N14, T17,
H14, K14
B2, C3, D4, D9, H8, H9, H10, J4, J8, J9, J10,
K8, K9, K10, P4, P9, P14, R3, R15, T2, T16
H15, H17
B16, C15, D14, J14
C16, C17, E16, F16, K15, L14, P17, R17
Device Digital Power.
PLL Power.
High-Speed Analog Transmitter Power.
High-Speed Analog Receiver Power.
Device Digital Ground.
V
SS
P
V
SS
T
V
SS
R
X
PLL Ground.
High-Speed Analog Transmitter Ground.
High-Speed Analog Receiver Ground.
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