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參數(shù)資料
| 型號： | LU5X34F |
| 廠商： | Lineage Power |
| 英文描述： | Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器) |
| 中文描述： | 四個千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)四收發(fā)器） |
| 文件頁數(shù)： | 23/26頁 |
| 文件大?。?/td> | 445K |
| 代理商： | LU5X34F |
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23
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Test Modes
(continued)
Table 18. Test Modes
(continued)
Global
Local Test Configuration
Global
OPERATION
BYPPLL
0
TEST1
0
TEST2
0
TEST3
1
TEST4
0
TEST5
Output
Transmitter is held in reset. BYPPLL
overrides this reset. Analog PLL feed-
back signal viewed at TEST5 pin.
Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data.
Transmitter and receiver are held in
reset. RX[9:0] output is from digital fil-
ter, not the serial data. Analog PLL
feedback signal viewed at TEST5 pin.
Analog PLL is bypassed for low speed
functional test. A low-speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5X REFCLK, but here REF-
CLK is lowered to about 1 MHz.
Analog PLL is bypassed for low-speed
functional test. A low-speed clock is
input to TEST4, and a quadrature clock
is applied to TEST5. Frequency of
clocks is 5X REFCLK, but here REF-
CLK is lowered to about 1 MHz.
RX[9:0] output is from digital filter, not
the serial data.
0
0
0
0
1
X
0
0
0
0
0
Output
1
X
X
1
C-0
C-90
1
X
X
0
C-0
C-90
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