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參數(shù)資料
| 型號： | LU5X34F |
| 廠商： | Lineage Power |
| 英文描述： | Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器) |
| 中文描述： | 四個(gè)千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)四收發(fā)器） |
| 文件頁數(shù)： | 11/26頁 |
| 文件大小： | 445K |
| 代理商： | LU5X34F |
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11
Lucent Technologies Inc.
Preliminary Data Sheet
July 2000
LU5X34F
Quad Gigabit Ethernet Transceiver
Input/Output Information
(continued)
Table 3c. Pinout—Channel C I/O
Name
Pin
T1
R2
P3
N4
R1
P2
N3
M4
P1
N2
P6
R5
U4
T5
R6
U5
T6
R7
P7
U6
U2
I/O
Input
Level
TTL/
CMOS
Description
TXC9
TXC8
TXC7
TXC6
TXC5
TXC4
TXC3
TXC2
TXC1
TXC0
RXC9
RXC8
RXC7
RXC6
RXC5
RXC4
RXC3
RXC2
RXC1
RXC0
TXCLKC
Channel C, Transmit Data [9:0].
Parallel input bits [9:0], one 10-bit, 8b/10b encoded
data byte, clocked in on the rising edge of TXCLKC.
TXC0 is the LSB.
Output
TTL/
CMOS
Channel C, Receive Data [9:0].
Parallel output bits [9:0], one 10-bit data type, clocked-
out on the alternate rising edge of RXCLK0C,
RXCLK1C. RXC0 is the LSB.
Input
TTL/
CMOS
Transmit Clock (100 MHz—125 MHz).
Used to latch TXC[9:0] data into the LU5X34F.
Synchronous with REFCLK(N)
Channel C, Byte-Align Clock 0.
RXCLK0C
P5
Output
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
TTL/
CMOS
PECL
RXCLK1C
R4
Output
Channel C, Byte-Align Clock 1.
ENCDETC
L1
Input
Channel C, Enable-Comma Detect.
COMDETC
T4
Output
Channel C, Byte-Aligned Comma.
EWRAPC
K3
Input
Channel C, Loopback at Serial I/O.
LCKREFNC
L4
Input
Channel C, Lock Receiver to Clock.
HDINCP
HDINCN
HDOUTCP
HDOUTCN
LDSTC
L16, M17
Input
Channel C, Differential Serial Inputs.
M15, M16
Output
PECL
Channel C, Differential Serial Outputs.
L2
Input
TTL/
CMOS
Channel C, Load Test[5:1] Inputs.
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