參數(shù)資料
型號(hào)： LU5X34F
廠商： Lineage Power
英文描述： Quad Gigabit Ethernet Transceiver(千兆位以太網(wǎng)四收發(fā)器)
中文描述： 四個(gè)千兆以太網(wǎng)收發(fā)器（千兆位以太網(wǎng)四收發(fā)器）
文件頁數(shù)： 2/26頁
文件大小： 445K
代理商： LU5X34F
2
Table of Contents
Lucent Technologies Inc.
Contents
Page
Table
Page
LU5X34F
Quad Gigabit Ethernet Transceiver
Preliminary Data Sheet
July 2000
Overview....................................................................1
Features.....................................................................1
Functional Description ...............................................3
Transmitter Section.................................................3
Receiver Section.....................................................3
Lock to Reference...................................................3
Byte Alignment........................................................4
Parallel Output Port.................................................4
Loopback Mode Operation......................................4
Powerup Sequence.................................................5
Device Reset...........................................................5
Sleep Mode.............................................................5
Block Diagrams.......................................................6
Block Diagrams (continued)....................................7
Input/Output Information............................................8
Electrical Specifications ...........................................14
Transmitter............................................................14
Receiver................................................................14
Receiver (continued).............................................15
Timing Characteristics .............................................16
Serial Timing.........................................................16
Receiver Section Timing.......................................17
Receiver Port Timing.............................................17
Transmitter Section Timing...................................18
Application Section ..................................................19
Test Modes..............................................................22
Outline Diagram.......................................................24
217-pin PBGA.......................................................24
Ordering Information................................................25
Table 1. Receive Circuit Operating Modes .............3
Table 2. Definition of Bit Transmission/Reception
Order ....................................................................4
Table 3a. Pinout—Channel A I/O............................9
Table 3b. Pinout—Channel B I/O..........................10
Table 3c. Pinout—Channel C I/O..........................11
Table 3d. Pinout—Channel D I/O .........................12
Table 3e. Pinout—Common I/O............................13
Table 3f. Pinout—Power I/O .................................13
Table 4. Reference Clock Specifications
(REFCLK and REFCLKN)..................................14
Table 5. PLL Specifications ..................................14
Table 6. Output Jitter at 1.0 Gbit/s—1.25 Gbits/s
Data Rate ...........................................................14
Table 7. Input Data Rate.......................................14
Table 8. Data Lock Characteristics.......................14
Table 9. Power Dissipation...................................15
Table 10. dc Electrical Specifications ...................15
Table 11. Absolute Maximum Ratings ..................15
Table 12. Serial Output Timing Levels..................16
Table 13. Serial Input Interface Timing ................16
Table 14. Receiver Parallel Port Timing ...............17
Table 15. Transmitter Timing at Parallel Interface 18
Table 16. External Resistor Value vs. Differential
Output Level Viewing .........................................20
Table 17. External Resistor Value vs. Differential
Output Level Viewing .........................................21
Table 18. Test Modes ...........................................22
Figure
Page
Figure 1. LU5X34F Quad Gigabit Ethernet Transceiver
Block Diagram........................................................ 6
Figure 2. LU5X34F Single-Channel Transceiver Func-
tional Diagram ........................................................ 7
Figure 3. Pin Designations (Top View) ..................... 8
Figure 4. Serial Interface Timing............................. 16
Figure 5. Receiver Section Timing.......................... 17
Figure 6. Receiver Port Timing ............................... 17
Figure 7. Parallel Interface Transmit Timing........... 18
Figure 8. Reference Clock Connections with Single-
Ended and Differential Sources............................ 19
Figure 9. Typical Termination for a Single-Channel,
High-Speed Serial Transmit-and-Receive Port in a
50
Backplane Application ................................. 20
Figure 10. Typical Termination for a Single-Channel,
High-Speed Serial Transmit Port Interfacing a 5 V
GBIC Transceiver................................................. 21
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