參數(shù)資料
型號(hào)： LTC4278IDKD#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 3/42頁(yè)
文件大?。?/td> 0K
描述： IC PD IEEE 802.3AT 25.5W 32-DFN
產(chǎn)品培訓(xùn)模塊： Power over Ethernet
標(biāo)準(zhǔn)包裝： 52
控制器類(lèi)型： 供電設(shè)備接口控制器（PD）
接口： IEEE 802.3af
電源電壓： 4.5 V ~ 20 V
電流 - 電源： 6.4mA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-DFN（7x4）裸露焊盤(pán)
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1338 (CN2011-ZH PDF)
LTC4278
11
4278fc
Information section for details. This pin is used for the
UVLO function of the switching regulator. The PD interface
section has an internal UVLO.
SENSE–, SENSE+ (Pins 19, 20): Current Sense Inputs.
These pins are used to measure primary-side switch cur-
rent through an external sense resistor. Peak primary-side
current is used in the converter control loop. Make Kelvin
connections to the sense resistor RSENSE to reduce noise
problems.SENSE–connectstotheGNDside.Atmaximum
current (VCMP at its maximum voltage) SENSE pins have
100mV threshold. The signal is blanked (ignored) during
the minimum turn-on time.
CCMP (Pin 21): Load Compensation Capacitive Control.
Connect a capacitor from CCMP to GND in order to reduce
the effects of parasitic resistances in the feedback sensing
path. A 0.1F ceramic capacitor suffices for most applica-
tions. Short this pin to GND when load compensation is
not needed.
RCMP (Pin 22): Load Compensation Resistive Control.
Connect a resistor from RCMP to GND in order to com-
pensate for parasitic resistances in the feedback sensing
path. In less demanding applications, this resistor is not
needed and this pin can be left open. See the Applications
Information section for details.
PIN FUNCTIONS
PGDLY (Pin 23): Primary Gate Delay Control. Connect an
external programming resistor (RPGDLY) to set delay from
synchronous gate turn-off to primary gate turn-on. See
the Applications Information section for details.
PG (Pin 24): Primary Gate Drive. PG is the gate drive pin
for the primary-side MOSFET switch. Large dynamic cur-
rents flow during voltage transitions. See the Applications
Information section for details.
VNEG (Pins 26, 27): System Negative Rail. Connects VNEG
to VPORTN through an internal power MOSFET. Pin 26 and
Pin 27 must be electrically tied together at the package.
PWRGD (Pin 29): Power Good Output, Open-Collector.
High impedance signals power-up completion. PWRGD
is referenced to VNEG and features a 14V clamp.
PWRGD (Pin 30): Complementary Power Good Output,
Open-Drain.Lowimpedancesignalspower-upcompletion.
PWRGD is referenced to VPORTN.
VPORTP (Pin 32): Positive Power Input. Tie to the input
port power through the input diode bridge.
Exposed Pad (Pin 33): Ground. This is the negative rail
connection for both signal ground and gate driver grounds
of the flyback controller. This pin should be connected to
VNEG.
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LTC4278IDKDTRPBF 制造商:LINER 制造商全稱(chēng):Linear Technology 功能描述:IEEE 802.3at PD with Synchronous No-Opto Flyback Controller and 12V Aux Support
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LTC4280CUFD#TRPBF 功能描述:IC CTLR HOT SWAP I2C MON 24QFN RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:119 系列:- 類(lèi)型:熱交換控制器 應(yīng)用:通用型，PCI Express? 內(nèi)部開(kāi)關(guān):無(wú) 電流限制:- 電源電壓:3.3V，12V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:80-TQFP 供應(yīng)商設(shè)備封裝:80-TQFP（12x12） 包裝:托盤(pán) 產(chǎn)品目錄頁(yè)面:1423 (CN2011-ZH PDF)
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