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| 型號： | LTC4278IDKD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 2/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PD IEEE 802.3AT 25.5W 32-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Power over Ethernet |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 控制器類型： | 供電設(shè)備接口控制器（PD） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 4.5 V ~ 20 V |
| 電流 - 電源： | 6.4mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1338 (CN2011-ZH PDF) |
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LTC4278
10
4278fc
PIN FUNCTIONS
SHDN (Pin 1): Shutdown Input. Use this pin for auxiliary
power application. Drive SHDN high to disable LTC4278
operation and corrupt the signature resistance. If unused,
tie SHDN to VPORTN.
T2P(Pin2):Type2PSEIndicator,Open-Drain.Lowimped-
ance indicates the presence of a Type 2 PSE.
RCLASS (Pin 3): Class Select Input. Connect a resistor
between RCLASS and VPORTN to set the classification load
current (see Table 2).
NC (Pins 4, 7, 8, 25, 28, 31): No Connect.
VPORTN (Pins 5, 6): Input Voltage, Negative Rail. Pin 5
and Pin 6 must be electrically tied together at the package.
SG (Pin 9): Synchronous Gate Drive Output. This pin
provides an output signal for a secondary-side synchro-
nous rectifier. Large dynamic currents may flow during
voltage transitions. See the Applications Information
section for details.
VCC (Pin 10): Supply Voltage Pin. Bypass this pin to
GND with a low ESR ceramic capacitor. See the Applica-
tions Information section for details.
tON (Pin 11): Pin for external programming resistor to
set the minimum time that the primary switch is on for
each cycle. Minimum turn-on facilitates the isolated feed-
back method. See the Applications Information section
for details.
ENDLY (Pin 12): Pin for external programming resistor to
set enable delay time. The enable delay time disables the
feedback amplifier for a fixed time after the turn-off of the
primary-side MOSFET. This allows the leakage inductance
voltage spike to be ignored for flyback voltage sensing.
See the Applications Information section for details.
SYNC (Pin 13): External Sync Input. This pin is used to
synchronize the internal oscillator with an external clock.
The positive edge of the clock causes the oscillator to dis-
charge causing PG to go low (off) and SG high (on). The
sync threshold is typically 1.5V. Tie to ground if unused.
See the Applications Information section for details.
SFST (Pin 14): Soft-Start. This pin, in conjunction with a
capacitor (CSFST) to GND, controls the ramp-up of peak
primary current through the sense resistor. It is also used
to control converter inrush at start-up. The SFST clamps
the VCMP voltage and thus limits peak current until soft-
start is complete. The ramp time is approximately 70ms
per F of capacitance. Leave SFST open if not using the
soft-start function.
OSC (Pin 15): Oscillator. This pin, in conjunction with an
external capacitor (COSC) to GND, defines the controller
oscillator frequency. The frequency is approximately
100kHz 100/COSC (pF).
FB (Pin 16): Feedback Amplifier Input. Feedback is usually
sensed via a third winding and enabled during the flyback
period.Thispinalsosinksadditionalcurrenttocompensate
for load current variation as set by the RCMP pin. Keep the
Thevenin equivalent resistance of the feedback divider at
roughly 3k.
VCMP (Pin 17): Frequency Compensation Control. VCMP
is used for frequency compensation of the switcher con-
trol loop. It is the output of the feedback amplifier and
the input to the current comparator. Switcher frequency
compensation components are placed on this pin to GND.
The voltage on this pin is proportional to the peak primary
switch current. The feedback amplifier output is enabled
during the synchronous switch on time.
UVLO (Pin 18): Undervoltage Lockout. A resistive divider
fromVPORTPtothispinsetsanundervoltagelockoutbased
upon VPORTP level (not VCC). When the UVLO pin is below
its threshold, the gate drives are disabled, but the part
draws its normal quiescent current from VCC.
The bias current on this pin has hysteresis such that the
bias current is sourced when UVLO threshold is exceeded.
Thisintroducesahysteresisatthepinequivalenttothebias
current change times the impedance of the upper divider
resistor. The user can control the amount of hysteresis
by adjusting the impedance of the divider. Tie the UVLO
pin to VCC if not using this function. See the Applications
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| LTC4278IDKDTRPBF | 制造商:LINER 制造商全稱:Linear Technology 功能描述:IEEE 802.3at PD with Synchronous No-Opto Flyback Controller and 12V Aux Support |
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