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| 型號： | LTC4278IDKD#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 29/42頁 |
| 文件大小： | 0K |
| 描述： | IC PD IEEE 802.3AT 25.5W 32-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Power over Ethernet |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 控制器類型： | 供電設(shè)備接口控制器（PD） |
| 接口： | IEEE 802.3af |
| 電源電壓： | 4.5 V ~ 20 V |
| 電流 - 電源： | 6.4mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1338 (CN2011-ZH PDF) |
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LTC4278
35
4278fc
APPLICATIONS INFORMATION
CMILLER is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 16).
The secondary-side power MOSFETs typically operate
at substantially lower VDS, so you can neglect transition
losses. The dissipation is calculated using:
PDIS(SEC) = IRMS(SEC)2 RDS(ON)(1 + d)
With power dissipation known, the MOSFETs’ junction
temperatures are obtained from the equation:
TJ = TA + PDIS θJA
whereTAistheambienttemperatureandθJAistheMOSFET
junction to ambient thermal resistance.
Once you have TJ iterate your calculations recomputing
d and power dissipations until convergence.
Gate Drive Node Consideration
The PG and SG gate drivers are strong drives to minimize
gate drive rise and fall times. This improves efficiency,
but the high frequency components of these signals can
cause problems. Keep the traces short and wide to reduce
parasitic inductance.
The parasitic inductance creates an LC tank with the
MOSFET gate capacitance. In less than ideal layouts, a
series resistance of 5Ω or more may help to dampen the
ringing at the expense of slightly slower rise and fall times
and poorer efficiency.
The LTC4278 gate drives will clamp the max gate voltage
to roughly 7.5V, so you can safely use MOSFETs with
maximum VGS of 10V and larger.
Synchronous Gate Drive
There are several different ways to drive the synchronous
gateMOSFET.Fullconverterisolationrequiresthesynchro-
nousgatedrivetobeisolated.Thisisusuallyaccomplished
by way of a pulse transformer. Usually the pulse driver is
used to drive a buffer on the secondary, as shown in the
application on the front page of this data sheet.
However,otherschemesarepossible.Therearegatedrivers
andsecondary-sidesynchronouscontrollersavailablethat
provide the buffer function as well as additional features.
QA
VGS
a
b
4278 F16
QB
MILLER EFFECT
GATE CHARGE (QG)
Figure 16. Gate Charge Curve
The flat portion of the curve is the result of the Miller (gate
to-drain)capacitanceasthedrainvoltagedrops.TheMiller
capacitance is computed as:
CMILLER =
QB –QA
VDS
The curve is done for a given VDS. The Miller capacitance
for different VDS voltages are estimated by multiplying the
computed CMILLER by the ratio of the application VDS to
the curve specified VDS.
WithCMILLERdetermined,calculatetheprimary-sidepower
MOSFET power dissipation:
PD(PRI) =IRMS(PRI)
2 R
DS(ON) 1+ δ
(
)+
VIN(MAX)
PIN(MAX)
DCMIN
RDR
CMILLER
VGATE(MAX) – VTH
fOSC
where:
RDR is the gate driver resistance (≈10Ω)
VTH is the MOSFET gate threshold voltage
fOSC is the operating frequency
VGATE(MAX) = 7.5V for this part
(1 +
d) is generally given for a MOSFET in the form of a
normalizedRDS(ON)vstemperaturecurve.Ifyoudon’thave
a curve, use
d = 0.005/°C ΔT for low voltage MOSFETs.
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