參數(shù)資料
型號(hào): LTC4274CUHF#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 23/28頁(yè)
文件大?。?/td> 702K
描述: IC CONTROLLER POE 38-QFN
標(biāo)準(zhǔn)包裝: 52
類(lèi)型: 以太網(wǎng)供電 PSE 控制器(PoE)
應(yīng)用: 供電設(shè)備(PSE)
內(nèi)部開(kāi)關(guān): 無(wú)
電流限制: 可調(diào)
電源電壓: 3 V ~ 4.3 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 38-QFN
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)裸露焊盤(pán)
包裝: 管件
LTC4274
23
4274fd
APPLICATIONS INFORMATION
V
DD
 provides power for most of the internal LTC4274
circuitry, and draws a maximum of 3mA. A ceramic de-
coupling cap of at least 0.1糉 should be placed from V
DD
 
to DGND, as close as practical to each LTC4274 chip.
Figure 16 shows a three component low dropout regulator
for a negative supply to DGND generated from the negative
V
EE
 supply. V
DD
 is tied to AGND and DGND is negative
referenced to AGND. This regulator drives a single LTC4274
device. In Figure 17, DGND is tied to AGND in this boost
converter circuit for a positive V
DD
 supply of 3.3V above
AGND. This circuit can drive multiple LTC4274 devices
and opto couplers.
V
EE
 is the main supply that provides power to the PD.
Because it supplies a relatively large amount of power and
is subject to significant current transients, it requires more
design care than a simple logic supply. For minimum IR
loss and best system efficiency, set V
EE
 near maximum
amplitude (57V), leaving enough margin to account for
transient over- or undershoot, temperature drift, and the
line regulation specs of the particular power supply used.
Bypass capacitance between AGND and V
EE
 is very impor-
tant for reliable operation. If a short circuit occurs at the
output port it can take as long as 1約 for the LTC4274 to
begin regulating the current. During this time the current
is limited only by the small impedances in the circuit and
a high current spike typically occurs, causing a voltage
transient on the V
EE
  supply and possibly causing the
LTC4274 to reset due to a UVLO fault. A 1糉, 100V X7R
capacitor placed near the V
EE
 pin is recommended to
minimize spurious resets.
Isolating the Serial Bus
The LTC4274 includes a split SDA pin (SDAIN and SD-
AOUT) to ease opto-isolation of the bidirectional SDA line.
IEEE 802.3 Ethernet specifications require that network
segments (including PoE circuitry) be electrically isolated
from the chassis ground of each network interface de-
vice. However, network segments are not required to be
Figure 17. Positive V
DD
 Boost Converter
Figure 16. Negative LDO to DGND
4274 F17
R54
56k
C79
2200pF
GND
ITH/RUN
LTC3803
V
CC
2
5
V
FB
1
3
NGATE
Q15
FDC2512
Q13
FMMT723
Q14
FMMT723
SENSE
6
4
V
EE
C74
100糉
6.3V
C75
10糉
16V
L3
100糎
SUMIDA CDRH5D28-101NC
R51
4.7k
1%
R53
4.7k
1%
R52
3.32k
1%
3.3V AT 400mA
R55
806?/DIV>
1%
R59
0.100?/DIV>
1%, 1W
R56
47.5k
1%
R57
1k
D28
B1100
R58
10?/DIV>
R60
10?/DIV>
C73
10糉
6.3V
L4
10糎
SUMIDA CDRH4D28-100NC
+
C77
0.22糉
100V
C78
0.22糉
100V
C76
10糉
63V
4274 F16
R5
750k
D1
CMHZ4687-4.3V
C1
0.1糉
Q2
CMPTA92
V
EE
V
DD
LTC4274
AGND
V
EE
AGND
DGND
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