參數(shù)資料
型號: LTC4274CUHF#PBF
廠商: Linear Technology
文件頁數(shù): 21/28頁
文件大?。?/td> 702K
描述: IC CONTROLLER POE 38-QFN
標(biāo)準(zhǔn)包裝: 52
類型: 以太網(wǎng)供電 PSE 控制器(PoE)
應(yīng)用: 供電設(shè)備(PSE)
內(nèi)部開關(guān):
電流限制: 可調(diào)
電源電壓: 3 V ~ 4.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 38-QFN
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)裸露焊盤
包裝: 管件
LTC4274
21
4274fd
APPLICATIONS INFORMATION
even at extended 802.3at power levels. Current limit and
foldback behavior are programmable. Figure 14 shows
MOSFET power dissipation with 802.3af-style foldback
compared with a typical MOSFET SOA curve; Figure 15
demonstrates how two-stage foldback keeps the FET
within its SOA under the same conditions. Table 5 gives
examples of recommended I
LIM
 register settings.
The LTC4274 will support current levels well beyond the
maximum values in the 802.3at specification. The shaded
areas in Table 5 indicate settings that may require a larger
external MOSFET, additional heat sinking, or a reduced
t
LIM
 setting.
MOSFET Fault Detection
The LTC4274 PSE port is designed to tolerate significant
levels of abuse, but in extreme cases it is possible for the
external MOSFET to be damaged. A failed MOSFET may
short source to drain, which will make the port appear to
be on when it should be off; this condition may also cause
the sense resistor to fuse open, turning off the port but
causing the LTC4274 SENSE pin to rise to an abnormally
high voltage. A failed MOSFET may also short from gate
to drain, causing the LTC4274 GATE pin to rise to an ab-
normally high voltage. The LTC4274 SENSE and GATE pins
are designed to tolerate up to 80V faults without damage.
If the LTC4274 sees any of these conditions for more than
180約, it disables all port functionality, reduces the gate
drive pull-down current for the port and reports a FET Bad
fault. This is typically a permanent fault, but the host can
attempt to recover by resetting the port, or by resetting
the entire chip if a port reset fails to clear the fault. If the
MOSFET is in fact bad, the fault will quickly return, and
the port will disable itself again.
An open or missing MOSFET will not trigger a FET Bad
fault, but will cause a t
START
 fault if the LTC4274 attempts
to turn on the port.
Voltage and Current Readback
The LTC4274 measures the output voltage and current
at the port with an internal A/D converter. Port data is
only valid when the port power is on. The converter has
two modes:
" Slow mode: 14 samples per second, 14.5 bits resolution
" Fast mode: 440 samples per second, 9.5 bits resolution
In fast mode, the least significant 5 bits of the lower byte
are zeroes so that bit scaling is the same in both modes.
Disconnect
The LTC4274 monitors the port to make sure that the PD
continues to draw the minimum specified current. A dis-
connect timer counts up whenever port current is below
7.5mA (typ), indicating that the PD has been disconnected.
If the t
DIS
 timer expires, the port will be turned off and
the disconnect bit in the fault event register will be set.
If the current returns before the t
DIS
 timer runs out, the
Figure 14. Turn On Currents vs FET Safe Operating
Area at 90癈 Ambient
Figure 15. LTC4274 Foldback vs FET Safe Operating
Area at 90癈 Ambient
PD Voltage (V) at V
PSE
 = 58V
0
0.0
0.2
0.4
0.6
10
20
30
40
4274 F14
50
0.8
1.0
0.1
0.3
0.5
0.7
0.9
60
802.3af FOLDBACK
SOA DC AT 90癈
PD Voltage (V) at V
PSE
 = 58V
0
0.0
0.2
0.4
0.6
10
20
30
40
4274 F15
50
0.8
1.0
0.1
0.3
0.5
0.7
0.9
60
802.3af FOLDBACK
SOA DC AT 90癈
S
O
A
 
7
5
m
s
 
A
T
 
9
0
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