參數(shù)資料
型號: LTC4274CUHF#PBF
廠商: Linear Technology
文件頁數(shù): 19/28頁
文件大?。?/td> 702K
描述: IC CONTROLLER POE 38-QFN
標準包裝: 52
類型: 以太網(wǎng)供電 PSE 控制器(PoE)
應(yīng)用: 供電設(shè)備(PSE)
內(nèi)部開關(guān):
電流限制: 可調(diào)
電源電壓: 3 V ~ 4.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 38-QFN
供應(yīng)商設(shè)備封裝: 38-QFN(5x7)裸露焊盤
包裝: 管件
LTC4274
19
4274fd
APPLICATIONS INFORMATION
the OUT pin and measuring the resulting current; it then
reports the discovered class in the Port Status register. If
the LTC4274 is in AUTO pin mode, it will additionally use
the classification result to set the I
CUT
 and I
LIM
 thresholds.
See the Reset and the AUTO/MID Pin section for more
information.
The classification circuitry is disabled when the port is
initially powered up with the AUTO pin low, in shutdown
mode, or when the corresponding Class Enable bit is
cleared.
802.3at 2-Event Classification
The 802.3at spec defines two methods of classifying a
Type 2 PD.
One method adds extra fields to the Ethernet LLDP data
protocol; although the LTC4274 is compatible with this
classification method, it cannot perform classification
directly since it doesnt have access to the data path.
LLDP classification requires the PSE to power the PD as
a standard 802.3af (Type 1) device. It then waits for the
host to perform LLDP communication with the PD and
update the PSE port data. The LTC4274 supports chang-
ing the I
LIM
 and I
CUT
 levels on the fly, allowing the host
to complete LLDP classification.
The second 802.3at classification method, known as
2-event classification or ping-pong, is fully supported by
the LTC4274. A Type 2 PD that is requesting more than
13W will indicate Class 4 during normal 802.3af classifica-
tion. If the LTC4274 sees Class 4, it forces the port to a
specified lower voltage (called the mark voltage, typically
9V), pauses briefly, and then re-runs classification to
verify the Class 4 reading (Figure 1). It also sets a bit in
the High Power Status register to indicate that it ran the
second classification cycle. The second cycle alerts the
PD that it is connected to a Type 2 PSE which can supply
Type 2 power levels.
2-event ping-pong classification is enabled by setting a bit
in the ports High Power Mode register. Note that a ping-
pong enabled port only runs the second classification cycle
when it detects a Class 4 device; if the first cycle returns
Class 0 to 3, the port assumes it is connected to a Type
1 PD and does not run the second classification cycle.
Invalid Type 2 Class Combinations
The 802.3at spec defines a Type 2 PD class signature as
two consecutive Class 4 results; a Class 4 followed by a
Class 0-3 is not a valid signature. In AUTO pin mode, the
LTC4274 will power a detected PD regardless of the clas-
sification results, with one exception: if the PD presents
an invalid Type 2 signature (Class 4 followed by Class 0
to 3), the LTC4274 will not provide power and will restart
the detection process. To aid in diagnosis, the Port Status
register will always report the results of the last class pulse,
so an invalid Class 4Class 2 combination would report
a second class pulse was run in the High Power Status
register (which implies that the first cycle found Class 4),
and Class 2 in the Port Status register.
POWER CONTROL
External MOSFET, Sense R Summary
The primary function of the LTC4274 is to control the
delivery of power to the PSE port. It does this by control-
ling the gate drive voltage of an external power MOSFET
while monitoring the current via an external sense resis-
tor and the output voltage at the OUT pin. This circuitry
serves to couple the raw V
EE
 input supply to the port in
a controlled manner that satisfies the PDs power needs
while minimizing power dissipation in the MOSFET and
disturbances on the V
EE
 backplane.
The LTC4274 is designed to use 0.25?sense resistors to
minimize power dissipation. It also supports 0.5?sense
resistors, which are the default when LTC4258/LTC4259A
compatibility is desired.
Inrush Control
Once the command has been given to turn on the port,
the LTC4274 ramps up the GATE pin of the ports external
MOSFET in a controlled manner. Under normal power-up
circumstances, the MOSFET gate will rise until the port
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