參數(shù)資料
型號: LTC4269IDKD-2#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: SWITCHING CONTROLLER, 560 kHz SWITCHING FREQ-MAX, PDSO32
封裝: 7 X 4 MM, PLASTIC, M0-229, DFN-32
文件頁數(shù): 9/34頁
文件大?。?/td> 383K
代理商: LTC4269IDKD-2#TR
LTC4269-2
42692fb
continues to power the PD load as long as the port volt-
age does not fall below the UVLO threshold. When the
LTC4269-2 port voltage falls below the UVLO threshold,
the PD is disconnected, and classification mode resumes.
C1 discharges through the LTC4269-2 circuitry.
COMPLEMENTARY POWER GOOD
When LTC4269-2 fully charges the load capacitor (C1),
power good is declared and the LTC4269-2 load can safely
begin operation. The LTC4269-2 provides complementary
power good signals that remain active during normal
operation and are deasserted when the port voltage falls
below the PoE UVLO threshold, when the voltage exceeds
the overvoltage lockout (OVLO) threshold, or in the event
of a thermal shutdown. See Figure 6.
The PWRGD pin features an open-collector output refer-
encedtoVNEGwhichcaninterfacedirectlywiththeSD_VSEC
pin. When power good is declared and active, the PWRGD
pin is high impedance with respect to VNEG. An internal
14V clamp limits the PWRGD pin voltage. Connecting
the PWRGD pin to the SD_VSEC pin prevents the DC/DC
converter from commencing operation before the PDI
interface completely charges the reservoir capacitor, C1.
The active low PWRGD pin connects to an internal, open-
drain MOSFET referenced to VPORTN and can interface
directly to the shutdown pin of a DC/DC converter product.
When power good is declared and active, the PWRGD pin
is low impedance with respect to VPORTN.
PWRGD PIN WHEN SHDN IS INVOKED
InPDapplicationswhereanauxiliarypowersupplyinvokes
the SHDN feature, the PWRGD pin becomes high imped-
ance. This prevents the PWRGD pin that is connected to
the “RUN” pin of the DC/DC converter from interfering
with the DC/DC converter operations when powered by
an auxiliary power supply.
OVERVOLTAGE LOCKOUT
The LTC4269-2 includes an Overvoltage Lockout (OVLO)
feature (Figure 5) which protects the LTC4269-2 and its
load from an overvoltage event. If the input voltage ex-
ceeds the OVLO threshold, the LTC4269-2 discontinues
PD operation. Normal operations resume when the input
voltage falls below the OVLO threshold and when C1 is
charged up.
VPORTP
C1
5F
MIN
VPORTN
VNEG
LTC4269-2
42692 F05
TO
PSE
UNDERVOLTAGE
OVERVOLTAGE
LOCKOUT
CIRCUIT
PD
LOAD
CURRENT-LIMITED
TURN ON
+
LTC4269-2
VPORTP – VPORTN POWER MOSFET
0V TO ON*
OFF
>ON*
ON
<UVLO*
OFF
>OVLO
OFF
*INCLUDES ON-UVLO HYSTERESIS
ON THRESHOLD 36.1V
UVLO THRESHOLD 30.7V
OVLO THRESHOLD 71.0V
Figure 5. LTC4269-2 Undervoltage and Overvoltage Lockout
42692 F06
BOLD LINE INDICATES HIGH CURRENT PATH
PWRGD
POWER
NOT
GOOD
INRUSH COMPLETE
ON < VPORTP < OVLO
AND NOT IN THERMAL SHUTDOWN
VPORTP < UVLO
VPORTP > OVLO
OR THERMAL SHUTDOWN
POWER
GOOD
28
PWRGD
LTC4269-2
29
VNEG
27
VNEG
26
VPORTN 6
VPORTN
OVLO
ON
UVLO
TSD
5
CONTROL
CIRCUIT
Figure 6. LTC4269-2 Power Good Functional and State Diagram
applicaTions inForMaTion
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