參數(shù)資料
型號(hào)： LTC4266IGW#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 4/30頁(yè)
文件大小： 0K
描述： IC CTRLR IEEE 802.3AT 36-SSOP
產(chǎn)品培訓(xùn)模塊： Power over Ethernet
標(biāo)準(zhǔn)包裝： 32
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： I²C，2 線串口
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-BSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 36-SSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1338 (CN2011-ZH PDF)
LTC4266
12
4266fd
PIN FUNCTIONS
RESET: Chip Reset, Active Low. When the RESET pin is
low, the LTC4266 is held inactive with all ports off and all
internal registers reset to their power-up states. When
RESET is pulled high, the LTC4266 begins normal opera-
tion. RESET can be connected to an external capacitor
or RC network to provide a power turn-on delay. Internal
filtering of the RESET pin prevents glitches less than 1μs
wide from resetting the LTC4266. Internally pulled up to
VDD.
MID: Midspan Mode Input. When high, the LTC4266 acts
as a midspan device. Internally pulled down to DGND.
INT: Interrupt Output, Open Drain. INT will pull low when
any one of several events occur in the LTC4266. It will
return to a high impedance state when bits 6 or 7 are set
in the Reset PB register (1Ah). The INT signal can be used
to generate an interrupt to the host processor, eliminating
the need for continuous software polling. Individual INT
events can be disabled using the Int Mask register (01h).
See LTC4266 Software Programming documentation for
more information. The INT pin is only updated between
I2C transactions.
SCL: Serial Clock Input. High impedance clock input for
the I2C serial interface bus. SCL must be tied high if not
used.
SDAOUT: Serial Data Output, Open Drain Data Output for
the I2C Serial Interface Bus. The LTC4266 uses two pins
to implement the bidirectional SDA function to simplify
optoisolation of the I2C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAOUT should be grounded or left floating if not used.
See Applications Information for more information.
SDAIN: Serial Data Input. High impedance data input for
the I2C serial interface bus. The LTC4266 uses two pins
to implement the bidirectional SDA function to simplify
optoisolation of the I2C bus. To implement a standard
bidirectional SDA pin, tie SDAOUT and SDAIN together.
SDAIN must be tied high if not used. See Applications
Information for more information.
AD3: Address Bit 3. Tie the address pins high or low to set
the I2C serial address to which the LTC4266 responds. This
address will be 010A3A2A1A0b. Internally pulled up to VDD.
AD2: Address Bit 2. See AD3.
AD1: Address Bit 1. See AD3.
AD0: Address Bit 0. See AD3.
NC, DNC: All pins identified with “NC” or “DNC” must be
left unconnected.
DGND: Digital Ground. DGND is the return for the VDD
supply.
VDD: Logic Power Supply. Connect to a 3.3V power supply
relative to DGND. VDD must be bypassed to DGND near
the LTC4266 with at least a 0.1μF capacitor.
SHDN1: Shutdown Port 1, Active Low. When pulled low,
SHDN1 shuts down port 1, regardless of the state of the
internal registers. Pulling SHDN1 low is equivalent to set-
ting the Reset Port 1 bit in the Reset Pushbutton register
(1Ah). Internal filtering of the SHDN1 pin prevents glitches
less than 1μs wide from reseting the port. Internally pulled
up to VDD.
SHDN2: Shutdown Port 2, Active Low. See SHDN1.
SHDN3: Shutdown Port 3, Active Low. See SHDN1.
SHDN4: Shutdown Port 4, Active Low. See SHDN1.
AGND: Analog Ground. AGND is the return for the VEE
supply.
SENSE4: Port 4 Current Sense Input. SENSE4 monitors
the external MOSFET current via a 0.5Ω or 0.25Ω sense
resistor between SENSE4 and VEE. Whenever the voltage
across the sense resistor exceeds the overcurrent detection
threshold VCUT, the current limit fault timer counts up. If
the voltage across the sense resistor reaches the current
limit threshold VLIM, the GATE4 pin voltage is lowered to
maintain constant current in the external MOSFET. See
Applications Information for further details. If the port is
unused, the SENSE4 pin must be tied to VEE.
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