I2C Timing Clock " />
參數(shù)資料
型號(hào)： LTC4266IGW#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 27/30頁(yè)
文件大小： 0K
描述： IC CTRLR IEEE 802.3AT 36-SSOP
產(chǎn)品培訓(xùn)模塊： Power over Ethernet
標(biāo)準(zhǔn)包裝： 32
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： I²C，2 線串口
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-BSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 36-SSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1338 (CN2011-ZH PDF)
LTC4266
6
4266fd
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I2C Timing
Clock Frequency
(Note 7)
l
1
MHz
t1
Bus Free Time
Figure 5 (Notes 7, 9)
l
480
ns
t2
Start Hold Time
Figure 5 (Notes 7, 9)
l
240
ns
t3
SCL Low Time
Figure 5 (Notes 7, 9)
l
480
ns
t4
SCL High Time
Figure 5 (Notes 7, 9)
l
240
ns
t5
Data Hold Time
Figure 5 (Notes 7, 9) Data into chip
Data out of chip
l
60
120
ns
t6
Data Set-Up Time
Figure 5 (Notes 7, 9)
l
80
ns
t7
Start Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
t8
Stop Set-Up Time
Figure 5 (Notes 7, 9)
l
240
ns
tr
SCL, SDAIN Rise Time
Figure 5 (Notes 7, 9)
l
120
ns
tf
SCL, SDAIN Fall Time
Figure 5 (Notes 7, 9)
l
60
ns
Fault Present to INT Pin Low
(Notes 7, 9, 10)
l
150
ns
Stop Condition to INT Pin Low
(Notes 7, 9, 10)
l
1.5
μs
ARA to INT Pin High Time
(Notes 7, 9)
l
1.5
μs
SCL Fall to ACK Low
(Notes 7, 9)
l
120
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 140°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
Note 3: All currents into device pins are positive; all currents out of device
pins are negative.
Note 4: The LTC4266 operates with a negative supply voltage (with respect
to ground). To avoid confusion, voltages in this data sheet are referred to
in terms of absolute magnitude.
Note 5: tDIS is the same as tMPDO defined by IEEE 802.3at.
Note 6: The LTC4266 digital interface operates with respect to DGND. All
logic levels are measured with respect to DGND.
Note 7: Guaranteed by design, not subject to test.
Note 8: The IEEE 802.3af specification allows a PD to present its
Maintain Power Signature (MPS) on an intermittent basis without being
disconnected. In order to stay powered, the PD must present the MPS for
tMPS within any tMPDO time window.
Note 9: Values measured at VILD(MAX) and VIHD(MIN).
Note 10: If fault condition occurs during an I2C transaction, the INT pin
will not be pulled down until a stop condition is present on the I2C bus.
Note 11: Load Characteristic of the LTC4266 during Mark:
7V < (AGND – VOUTn) < 10V or IOUT < 50μA
Note 12: See the LTC4266 Software Programming documentation for
information on serial bus usage and device configuration and status
registers.
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. AGND – VEE = 54V, AGND = DGND, and VDD – DGND = 3.3V unless
otherwise noted. (Notes 3, 4)
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