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參數(shù)資料
型號(hào)： LTC4266IGW#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/30頁(yè)
文件大小： 0K
描述： IC CTRLR IEEE 802.3AT 36-SSOP
產(chǎn)品培訓(xùn)模塊： Power over Ethernet
標(biāo)準(zhǔn)包裝： 32
控制器類型： 以太網(wǎng)控制器（IEEE 802.3）
接口： I²C，2 線串口
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 36-BSOP（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 36-SSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 1338 (CN2011-ZH PDF)
LTC4266
25
4266fd
Four commonly available 1Ω resistors (0402 or larger
package size) can be used in parallel in place of a single
0.25Ω resistor. In order to meet the ICUT and ILIM accuracy
required by the IEEE specification, the sense resistors
should have ±1% tolerance or better, and no more than
±200ppm/°C temperature coefficient.
Output Cap
Each port requires a 0.22μF cap across its outputs to keep
the LTC4266 stable while in current limit during startup
or overload. Common ceramic capacitors often have sig-
nificant voltage coefficients; this means the capacitance
is reduced as the applied voltage increases. To minimize
this problem, X7R ceramic capacitors rated for at least
100V are recommended.
ESD/Cable Discharge Protection
Ethernet ports can be subject to significant ESD events
when long data cables, each potentially charged to thou-
sands of volts, are plugged into the low impedance of the
RJ45 jack. To protect against damage, each port requires a
pair of clamp diodes; one to AGND and one to VEE (Figure
10). An additional surge suppressor is required for each
LTC4266 chip from VEE to AGND. The diodes at the ports
steer harmful surges into the supply rails, where they are
absorbed by the surge suppressor and the VEE bypass
capacitance. The surge suppressor has the additional
benefit of protecting the LTC4266 from transients on the
VEE supply.
S1B diodes work well as port clamp diodes, and an
SMAJ58A or equivalent is recommended for the VEE surge
suppressor.
LAYOUT GUIDELINES
Standard power layout guidelines apply to the LTC4266:
place the decoupling caps for the VDD and VEE supplies
near their respective supply pins, use ground planes, and
use wide traces wherever there are significant currents.
The main layout challenge involves the arrangement of
the current sense resistors, and their connections to
the LTC4266. Because the sense resistor values are very
low, layout parasitics can cause significant errors. Care is
required to achieve specified accuracy, particularly with
disconnect currents.
Figure 19 illustrates the problem. In the example on the
left, two ports have load currents I1 and I2 that return to
the VEE power supply through a mutual resistance RM.
RM represents the combined resistances of any traces,
planes, and vias in the PCB that I1 and I2 share as they
return to the VEE supply. The LTC4266 measures the volt-
age difference between its SENSE and VEE pins to sense
the voltage drop across RS1, but as the example shows,
RM introduces errors.
The example on the right shows how errors can be
minimized with a good layout. The circuit is rearranged
so that RM no longer affects VS, and the VEE connection
to the LTC4266 is used as a Kelvin sense trace. VEE is not
APPLICATIONS INFORMATION
RM
+
VS
+
VS
RS1
MUTUAL RESISTANCE
RS2
4266 F19
IEE
––
I1 I2
I1 + I2 + IEE
VS = I1RS1 + I1RM + I2RM
LTC4266
GATE
SENSE
SIGNAL
SCALE ERROR
CROSSTALK ERROR
VEE
RK
RM
RS1
KELVIN SENSE LINE
RS2
IEE
I1 I2
VS = I1RS1 – IEERK
I1 + I2 + IEE
LTC4266
GATE
SENSE
SIGNAL
SMALL OFFSET ERROR
VEE
Figure 19. Layout Affects Current Readback Accuracy
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