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參數(shù)資料
| 型號(hào)： | LTC4266IGW#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/30頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CTRLR IEEE 802.3AT 36-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Power over Ethernet |
| 標(biāo)準(zhǔn)包裝： | 32 |
| 控制器類型： | 以太網(wǎng)控制器（IEEE 802.3） |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-BSOP（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1338 (CN2011-ZH PDF) |
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LTC4266
26
4266fd
U1
LTC4266
PORTS A THROUGH D
SENSE1
SENSE2
SENSE3
SENSE4
VEE
VIA
4266 F20
BY KEEPING THESE COPPER FILLS SEPARATE ON
THE SURFACE, MUTUAL RESISTANCE BETWEEN
PORTS A-D AND E-H IS ELIMINATED
THIS TRACE PROVIDES VEE TO U1
BUT ALSO ACTS AS A KELVIN
SENSE LINE FOR PORTS A-D
VEE COPPER FILL ON SURFACE LAYER
VEE PLANE ON INNER LAYER
U2
LTC4266
PORTS E THROUGH H
SENSE1
SENSE2
SENSE3
SENSE4
VEE
RSENSE
RETURN TO
VEE POWER SUPPLY
Figure 20. Layout Strategy to Reduce Mutual Resistance
APPLICATIONS INFORMATION
a perfect Kelvin connection because all four ports con-
trolled by the LTC4266 share the same sense trace, and
because the current through the trace (IEE) is not zero.
However, as the equation shows, the remaining error is a
small offset term.
Figure 20 shows two LTC4266 chips controlling eight ports
(A though H). The ports are separated into two groups
of four; each has its own trace on the top PCB layer that
connects to the VEE plane with a via. Currents from the U1
sub-circuit are effectively isolated from the U2 sub-circuit,
reducing the layout problem down to 4-port chunks; this
arrangement can be expanded for any number of ports.
Figure 21 shows an example of good 4-port layout. Each
0.25Ω sense resistor consists of four 1Ω resistors in
parallel. The four groups of resistors are arranged to
minimize the overlap in their current flows, which mini-
mizes mutual resistance. The horizontal slits cut in the
copper help to keep the currents separate. Wide copper
paths connect each group of resistors to the vias at the
center, so the resistance is very low.
Proper connection of the sense line is also important. In
Figure 21, U1 is not connected directly to the VEE plane
but is connected instead to a Kelvin sense trace that
leads to the sense resistor array. Similarly, the via at the
center of the sense resistor array has a matching hole
in the VEE plane. This arrangement prevents the mutual
resistance of the four large vias from influencing the
current measurements.
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