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參數(shù)資料
| 型號(hào)： | LTC4252 |
| 廠商： | Linear Technology Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Negative 48V Hot Swap Controller |
| 中文描述： | 負(fù)48V熱插拔控制器 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大小： | 327K |
| 代理商： | LTC4252 |
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LTC4252-1/LTC4252-2
9
425212f
V
EE
(Pin 5/Pin 4):
Negative Supply Voltage Input. Connect
this pin to the negative side of the power supply.
GATE (Pin 6/Pin 5):
N-Channel MOSFET Gate Drive Out-
put. This pin is pulled high by a 58
μ
A current source. GATE
is pulled low by invalid conditions at V
IN
(UVLO), UV, OV,
or a circuit breaker fault timeout. GATE is actively servoed
to control the fault current as measured at SENSE. A
compensation capacitor at GATE stabilizes this loop. A
comparator monitors GATE to ensure that it is low before
allowing an initial timing cycle, GATE ramp-up after an
overvoltage event or restart after a current limit fault.
During GATE start-up, a second comparator detects if
GATE is within 2.8V of V
IN
before PWRGD is set (MS
package only).
DRAIN (Pin7/Pin 6):
Drain Sense Input. Connecting an
external resistor, R
D
,
between this pin and the MOSFET’s
drain (V
OUT
) allows voltage sensing below 6.15V and
current feedback to TIMER. A comparator detects if DRAIN
is below 2.385V and together with the GATE high com-
parator sets the PWRGD flag. If V
OUT
is above V
DRNCL
,
DRAIN clamps at approximately V
DRNCL
. The current
through R
D
is internally multiplied by 8 and added to
TIMER’s 230
μ
A pullup current during a circuit breaker
fault cycle. This reduces the fault time and MOSFET
heating.
OV (Pin 8/Pin7):
Overvoltage Input. The active high thresh-
old at the OV pin is set at 6.15V with 0.6V hysteresis. If OV
> 6.15V, GATE pulls low. When OV returns below 5.55V,
GATE start-up begins without an initial timing cycle. If an
overvoltage condition occurs in the middle of an initial
timing cycle, the initial timing cycle is restarted after the
overvoltage condition goes away. An overvoltage condi-
tion does not reset the PWRGD flag. The internal UVLO at
V
IN
always overrides OV. A 1nF to 10nF capacitor at OV
prevents transients and switching noise from affecting the
OV thresholds and prevents glitches at the GATE pin.
UV (Pin 9/Pin 7):
Undervoltage Input. The active low
threshold at the UV pin is set at 2.925V with 0.3V hyster-
esis. If UV < 2.925V, PWRGD pulls high, both GATE and
TIMER pull low. If UV rises above 3.225V, this initiates an
initial timing cycle followed by GATE start-up. The internal
UVLO at V
IN
always overrides UV. A low at UV resets an
internal fault latch. A 1nF to 10nF capacitor at UV prevents
transients and switching noise from affecting the UV
thresholds and prevents glitches at the GATE pin.
TIMER (Pin 10/Pin 8):
Timer Input. TIMER is used to
generate an initial timing delay at start-up and to delay
shutdown in the event of an output overload (circuit
breaker fault). TIMER starts an initial timing cycle when
the following conditions are met: UV is high, OV is low, V
IN
clears UVLO, TIMER pin is low, GATE is lower than V
GATEL
,
SS < 0.2V, and V
SENSE
– V
EE
< V
CB
. A pull-up current of
5.8
μ
A then charges C
T
, generating a time delay. If C
T
charges to V
TMRH
(4V), the timing cycle terminates, TIMER
quickly pulls low and GATE is activated.
If SENSE exceeds 50mV while GATE is high, a circuit
breaker cycle begins with a 230
μ
A pull-up current charg-
ing C
T
. If DRAIN is approximately 7V during this cycle, the
timer pull-up has an additional current of 8 I
DRN
. If SENSE
drops below 50mV before TIMER reaches 4V, a 5.8
μ
A
pull-down current slowly discharges the C
T
. In the event
that C
T
eventually integrates up to the V
TMRH
threshold,
the circuit breaker trips, GATE quickly pulls low and
PWRGD pulls high. The LTC4252-1 TIMER pin latches
high with a 5.8
μ
A pull-up source. This latched fault is
cleared by either pulling TIMER low with an external device
or by pulling UV below 2.925V. The LTC4252-2 the starts
a shutdown cooling cycle following an overcurrent fault.
This cycle consists of 4 discharging ramps and 3 charging
ramps. The charging and discharging currents are 5.8
μ
A
and TIMER ramps between its 1V and 4V thresholds. At the
completion of a shutdown cooling cycle, the LTC4252-2
attempts a start-up cycle.
PIU
(MS/MS8)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC4252-1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers |
| LTC4252-1_12 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Negative Voltage Hot Swap Controllers |
| LTC4252-1A | 制造商:LINER 制造商全稱:Linear Technology 功能描述:Negative Voltage Diode-OR Controller |
| LTC42521CMS | 制造商:Linear Technology 功能描述: |
| LTC4252-1CMS | 功能描述:IC CNTRLR HOTSWAP NEGVOLT 10MSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 類型:熱交換控制器 應(yīng)用:-48V 遠(yuǎn)程電力系統(tǒng)，AdvancedTCA ? 系統(tǒng)，高可用性 內(nèi)部開關(guān):無 電流限制:可調(diào) 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
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