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LTC4252-1/LTC4252-2
18
425212f
The maximum current flowing in the DRAIN pin is given
by:
I
V
V
R
DRN MAX
(
SUPPLY MAX
DRNCL
D
)
(
)
=
(12)
Approximating a linear charging rate as I
DRN
drops from
I
DRN(MAX)
to zero, the I
DRN
component in Equation (3) can
be approximated with 0.5 I
DRN(MAX)
. Rearranging equa-
tion, TIMER capacitor C
T
is given by:
(
(
)
4
Returning to Equation (3), the TIMER period is calculated
and used in conjunction with V
SUPPLY(MAX)
and
I
SHORTCIRCUIT(MAX)
to check the SOA curves of a prospec-
tive MOSFET.
As a numerical design example, consider a 30W load,
which requires 1A input current at 36V. If V
SUPPLY(MAX)
=
72V and C
L
= 100
μ
F, R
D
= 1M
, Equation (8) gives R
S
=
40m
; Equation (13) gives C
T
= 441nF. To account for
errors in R
S
, C
T
, TIMER current (230
μ
A), TIMER threshold
(4V), R
D
, DRAIN current multiplier and DRAIN voltage
clamp (V
DRNCL
), the calculated value should be multiplied
by 1.5, giving the nearest standard value of C
T
= 680nF.
If a short-circuit occurs, a current of up to 120mV/
40m
=3A will flow in the MOSFET for 3.6ms as dictated
by C
T
=680nF in Equation (3). The MOSFET must be
selected based on this criterion. The IRF530S can handle
100V and 3A for 10ms and is safe to use in this application.
Computing the maximum soft-start capacitor value during
soft-start to a load short is complicated by the nonlinear
MOSFET’s SOA characteristics and the R
SS
C
SS
response.
An overly conservative but simple approach begins with
the maximum circuit breaker current, given by:
mV
R
S
C
t
A
I
V
T
CL CHARGE
DRN MAX
(
=
μ +
)
)
230
4
(13)
I
CB MAX
(
)
=
60
(14)
From the SOA curves of a prospective MOSFET, determine
the time allowed, t
SOA(MAX)
. C
SS
is given by:
t
R
SS
.
0 916
In the above example, 60mV/40m
gives 1.5A. t
SOA(MAX)
for the IRF530S is 40ms. From Equation (15),
C
SS
= 437nF. Actual board evaluation showed that
C
SS
= 100nF was appropriate. The ratio (R
SS
C
SS
) to
t
CL(CHARGE)
is a good gauge as a large ratio may result in
the time-out period expiring. This gauge is determined
empirically with board level evaluation.
C
SS
SOA MAX
(
=
)
(15)
SUMMARY OF DESIGN FLOW
To summarize the design flow, consider the application
shown in Figure 2. It was designed for 50W.
Calculate the maximum load current: 50W/36V = 1.4A;
allowing for 83% converter efficiency, I
IN(MAX)
= 1.7A.
Calculate R
S
: from Equation (8) R
S
= 20m
.
Calculate I
SHORTCIRCUIT(MAX)
: from Equation (9)
I
SHORTCIRCUIT(MAX)
= 6A.
Select a MOSFET that can handle 6A at 72V: IRF530S.
Calculate C
T
: from Equation (13) C
T
= 220nF. Select
C
T
=330nF, which gives the circuit breaker time-out pe-
riod t
MAX
= 1.76ms.
Consult MOSFET SOA curves: the IRF530S can handle 6A
at 72V for 5ms, so it is safe to use in this application.
Calculate C
SS
: using Equations (14) and (15) select
C
SS
=68nF.
FREQUENCY COMPENSATION
The LTC4252 typical frequency compensation network for
the analog current limit loop is a series R
C
(10
) and C
C
connected to V
EE
. Figure 6 depicts the relationship be-
tween the compensation capacitor C
C
and the MOSFET’s
C
ISS
. The line in Figure 6 is used to select a starting value
APPLICATIU
W
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