
LTC4252-1/LTC4252-2
8
425212f
TYPICAL PERFOR AU
t
SS
vs Temperature
V
IN
(Pin 1/Pin 1):
Positive Supply Input. Connect this pin
to the positive side of the supply through a dropping
resistor. A shunt regulator clamps V
IN
at 13V. An internal
undervoltage lockout (UVLO) circuit holds GATE low until
the V
IN
pin is greater than V
LKO
(9.2V), overriding UV and
OV. If UV is high, OV is low and V
IN
comes out of UVLO,
TIMER starts an initial timing cycle before initiating a GATE
ramp-up. If V
IN
drops below approximately 8.2V, GATE
pulls low immediately.
PWRGD (Pin 2/Not Available):
Power Good Status Out-
put (MS only). At start-up, PWRGD latches low if DRAIN
is below 2.385V and GATE is within 2.8V of V
IN
. PWRGD
status is reset by UV, V
IN
(UVLO) or a circuit breaker fault
timeout. This pin is internally pulled high by a 58
μ
A current
source.
SS (Pin 3/Pin 2):
Soft-Start Pin. This pin is used to ramp
inrush current during start up, thereby effecting control
over di/dt. A 20x attenuated version of the SS pin voltage
is presented to the current limit amplifier. This attenuated
voltage limits the MOSFET’s drain current through the
sense resistor during the soft-start current limiting. At the
beginning of a start-up cycle, the SS capacitor (C
SS
) is
ramped by a 22
μ
A current source. The GATE pin is held
low until SS exceeds 20 V
OS
= 0.2V. SS is internally
shunted by a 100k resistor (R
SS
) which limits the SS pin
voltage to 2.2V. This corresponds to an analog current
limit SENSE voltage of 100mV. If the SS capacitor is
omitted, the SS pin ramps from 0V to 2.2V in about 220
μ
s.
The SS pin is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
SENSE (Pin 4/Pin 3):
Circuit Breaker/Current Limit Sense
Pin. Load current is monitored by a sense resistor R
S
connected between
SENSE and V
EE
, and controlled in
three steps.
If SENSE exceeds V
CB
(50mV), the circuit
breaker comparator activates a (230
μ
A+8I
DRN
) TIMER
pull-up current. If SENSE exceeds V
ACL
(100mV), the
analog current limit amplifier pulls GATE down to regulate
the MOSFET current at V
ACL
/R
S
. In the event of a cata-
strophic short-circuit, SENSE may overshoot 100mV. If
SENSE reaches V
FCL
(200mV), the fast current limit com-
parator pulls GATE low with a strong pull-down. To disable
the circuit breaker and current limit functions, connect
SENSE
to V
EE
.
PIU
I
PGH
vs Temperature
t
PLLUG
and t
PHLOG
vs Temperature
TEMPERATURE
°
(C)
–55 –35 –15
5
25
45
65
85 105 125
I
P
μ
A
4252-1/2 G38
62
61
60
59
58
57
56
55
V
PWRGD
= 0V
(MS ONLY)
TEMPERATURE (
°
C)
–55 –35 –15
5
25
45
65
85 105 125
t
S
μ
s
4252-1/2 G27
220
210
200
190
180
170
160
150
SS PIN FLOATING,
V
SS
RAMPS FROM 0.2V TO 2V
TEMPERATURE (
°
C)
–55
D
μ
s
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
–15
25
45
125
4252-1/2 G24
–35
5
65
85 105
t
PLLUG
t
PHLOG
(MS/MS8)