![](http://datasheet.mmic.net.cn/330000/LTC4252-1_datasheet_16430500/LTC4252-1_11.png)
LTC4252-1/LTC4252-2
11
425212f
4252-1/2 F01
LTC4252
C
LOAD
ISOLATED
DC/DC
CONVERTER
MODULE
–
LOW
VOLTAGE
CIRCUITRY
+
+
–
PLUG-IN BOARD
BACKPLANE
–48RTN
–48V
LONG
LONG
+
4252-1/2 F02
–48RTN
–48V
UV/OV
TIMER
V
EE
V
IN
SENSE
GATE
SS
DRAIN
LTC4252-1
R1
402k
1%
R2
32.4k
1%
R
D
1M
C
0.33
μ
F
C
SS
68nF
C
C
18nF
R
S
0.02
Q1
IRF530S
R
C
10
R
IN
10k
1
7
8
2
6
5
3
4
C1
10nF
C
IN
1
μ
F
C
LOAD
100
F
TYP
LONG
LONG
SHORT
+
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4252 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
Initial Start-Up
The LTC4252 resides on a removable circuit board and
controls the path between the connector and load or
power conversion circuitry with an external MOSFET switch
(see Figure 1). Both inrush control and short-circuit pro-
tection are provided by the MOSFET.
A detailed schematic is shown in Figure 2. –48V and
–48RTN receive power through the longest connector
pins and are the first to connect when the board is inserted.
The GATE pin holds the MOSFET off during this time. UV/
OV determines whether or not the MOSFET should be
turned on based upon internal high accuracy thresholds
and an external divider. UV/OV does double duty by also
monitoring whether or not the connector is seated. The top
of the divider detects –48RTN by way of a short connector
pin that is the last to mate during the insertion sequence.
OPERATIOU
Figure 1. Basic LTC4252 Hot Swap Topology
Figure 2. –48V, 2.5A Hot Swap Controller
Interlock Conditions
A start-up sequence commences once these “interlock”
conditions are met.
1. The input voltage V
IN
exceeds 9.2V (UVLO).
2. The voltage at UV > 3.225V.
3. The voltage at OV < 5.55V.
4. The (SENSE – V
EE
) voltage is < 50mV (V
CB
).
5. The voltage at SS is < 0.2V (20 V
OS
).
6. The voltage on the TIMER capacitor (C
T
) is < 1V (V
TMRL
).
7. The voltage at GATE is < 0.5V (V
GATEL
).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5.8
μ
A
into C
T
. If V
IN
, UV or OV falls out of range, the start-up cycle
stops and TIMER discharges C
T
to less than 1V, then waits
until the aforementioned conditions are once again met. If
C
T
successfully charges to 4V, TIMER pulls low and both
SS and GATE pins are released. GATE sources 58
μ
A
(I
GATE
), charging the MOSFET gate and associated capaci-
tance. The SS voltage ramp limits V
SENSE
to control the
inrush current. PWRGD pulls active low when GATE is
within 2.8V of V
IN
and DRAIN is lower than V
DRNL
.