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LTC4252-1/LTC4252-2
28
425212f
Soft-Start
If the SS pin is not connected, this pin defaults to a linear
voltage ramp, from 0V to 2.2V in about 220
μ
s at GATE
start-up, as shown in Figure 17a. If a soft-start capacitor,
C
SS
, is connected to this SS pin, the soft-start response is
modified from a linear ramp to an RC response (Equa-
tion6), as shown in Figure 17b. This feature allows load
current to slowly ramp-up at GATE start-up. Soft-start is
initiated at time point 3 by a TIMER transition from V
TMRH
to V
TMRL
(time points 1 to 2) or by the OV pin falling below
the V
OVLO
threshold after an OV condition. When the SS
pin is below 0.2V, the analog current limit amplifier holds
GATE low. Above 0.2V, GATE is released and 58
μ
A ramps
up the compensation network and GATE capacitance at
time point 4. Meanwhile, the SS pin voltage continues to
ramp up. When GATE reaches the MOSFET’s threshold,
the MOSFET begins to conduct. Due to the MOSFET’s high
g
m
, the MOSFET current quickly reaches the soft-start
control value of V
ACL
(t) (Equation 7). At time point 6, the
GATE voltage is controlled by the current limit amplifier.
The soft-start control voltage reaches the circuit breaker
voltage, V
CB
, at time point 7 and the circuit breaker TIMER
activates. As the load capacitor nears full charge, load
current begins to decline below V
ACL
(t). The current limit
loop shuts off and GATE releases at time point 8. At time
point9, the SENSE voltage falls below V
CB
and TIMER
deactivates.
Large values of C
SS
can cause premature circuit breaker
time out as V
ACL
(t) may exceed the V
CB
potential during
the circuit breaker delay. The load capacitor is unable to
achieve full charge in one GATE start-up cycle. A more
serious side effect of large C
SS
values is SOA duration may
be exceeded during soft-start into a low impedance load.
A soft-start voltage below V
CB
will not activate the circuit
breaker TIMER.
Figure 17. Soft-Start Timing (All Waveforms are Referenced to V
EE
)
(17a) Without External C
SS
(17b) With External C
SS
TIMER
GATE
SENSE
SS
DRAIN
V
TMRH
V
DRNCL
V
ACL
V
CB
V
DRNL
V
GS(th)
V
IN
– V
GATEH
V
TMRL
230
μ
A + 8 I
DRN
4252-1/2 F17
PWRGD
5.8
μ
A
58
μ
A
58
μ
A
TIMER
GATE
SENSE
SS
DRAIN
V
TMRH
V
DRNCL
V
CB
V
ACL
V
DRNL
V
GS(th)
V
IN
– V
GATEH
V
TMRL
230
μ
A + 8 I
DRN
PWRGD
5.8
μ
A
58
μ
A
58
μ
A
12 34 567
7a
8 9
10
11
END OF INTIAL TIMING CYCLE
12 34 5 6
7
8 9
10
11
END OF INTIAL TIMING CYCLE
20 V
OS
20 (V
CB
+ V
OS
)
20 (V
ACL
+ V
OS
)
20 V
OS
20 (V
CB
+ V
OS
)
20 (V
ACL
+ V
OS
)
APPLICATIU
W
U
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