參數(shù)資料
型號: LTC4252-2CMS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: Negative Voltage Hot Swap Controllers
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: PLASTIC, MSOP-8
文件頁數(shù): 19/32頁
文件大小: 327K
代理商: LTC4252-2CMS8
LTC4252-1/LTC4252-2
19
425212f
for C
C
based upon the MOSFET’s C
ISS
specification. Opti-
mized values for C
C
are shown for several popular
MOSFETs. Differences in the optimized value of C
C
versus
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
As seen in Figure 5 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4252’s
V
EE
and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4252 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
V
OUT
and DRAIN. V
IN
and PWRGD follow at a slower rate
as set by the V
IN
bypass capacitor. At time point 2, V
IN
exceeds V
LKO
and the internal logic checks for UV > V
UVHI
,
OV < V
OVLO
, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 V
OS
and TIMER < V
TMRL
. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5.8
μ
A current source pull-up. At time point 3, TIMER
reaches the V
TMRH
threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the V
TMRL
threshold is reached and the
conditions of GATE < V
GATEL
, SENSE < V
CB
and
SS<20V
OS
must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by R
SS
C
SS
(as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 V
OS
. Upon releasing
GATE, 58
μ
A sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFET’s threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
APPLICATIU
W
U
U
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO –48V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
V
EE
4252-1/2 F07
Figure 7. Making PCB Connections to the Sense Resistor
MOSFET C
ISS
(pF)
0
C
C
60
50
40
30
20
10
0
2000
4000
4252-1/2 F06
6000
8000
NTY100N10
IRF3710
IRF540
IRF530
IRF740
Figure 6. Recommended Compensation
Capacitor C
C
vs MOSFET C
ISS
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