參數(shù)資料
型號(hào)： LTC4252-2CMS8
廠商： LINEAR TECHNOLOGY CORP
元件分類： 電源管理
英文描述： Negative Voltage Hot Swap Controllers
中文描述： 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝： PLASTIC, MSOP-8
文件頁(yè)數(shù)： 15/32頁(yè)
文件大?。?/td> 327K
代理商： LTC4252-2CMS8
LTC4252-1/LTC4252-2
15
425212f
period, the charging of C
T
accelerates by 8 I
DRN
of
Equation (1).
Intermittent overloads may exceed the 50mV threshold at
SENSE, but, if their duration is sufficiently short, TIMER
will not reach 4V and the LTC4252 will not shut the external
MOSFET off. To handle this situation, the TIMER dis-
charges C
T
slowly with a 5.8
μ
A pull-down whenever the
SENSE voltage is less than 50mV. Therefore, any intermit-
tent overload with V
OUT
< 6.15V and an aggregate duty
cycle of 2.5% or more will eventually trip the circuit
breaker and shut down the LTC4252. Figure 4 shows the
circuit breaker response time in seconds normalized to
1
μ
F for I
DRN
= 0
μ
A. The asymmetric charging and dis-
charging of C
T
is a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
t
(
C
F
I
D
T
DRN
)
.
.
μ
=
+
(
)
[
]
4
235 8
8
5 8
(4)
a shutdown cooling cycle begins if TIMER reaches the 4V
threshold. TIMER starts with a 5.8
μ
A pull-down until it
reaches the 1V threshold. Then, the 5.8
μ
A pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8
μ
A
pull-down cycles and three 5.8
μ
A pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
t
V C
μ
5 8
.
A
SHUTDOWN
T
=
7 3
(5)
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFET’s SOA rating if powering up into an active load. If
SS floats, an internal current source ramps SS from 0V to
2.2V in about 220
μ
s. Connecting an external capacitor C
SS
from SS to ground modifies the ramp to approximate an
RC response of:
V
t
V
e
SS
SS
t
R
C
SS
SS
()
≈
1
(6)
An internal resistor divider (95k/5k) scales V
SS
(t) down by
20 times to give the analog current limit threshold:
V
t
V
t
V
ACL
SS
20
OS
()
()
=
(7)
This allows the inrush current to be limited to V
ACL
(t)/R
S
.
The offset voltage, V
OS
(10mV), ensures C
SS
is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
APPLICATIU
W
U
U
FAULT DUTY CYCLE (%)
0
20
40
60
80
100
N
μ
F
10
1
0.1
0.01
4252-1/2 F04
=
4
[(235.8 + 8 I
DRN
) D – 5.8]
t
C
T
(
μ
F)
I
DRN
= 0
μ
A
Figure 4. Circuit-Breaker Response Time
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8
μ
A pull-up after the circuit breaker fault TIMER
reaches 4V. For the LTC4252-2 (automatic retry version),
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