參數(shù)資料
型號: LTC4252-2CMS8
廠商: LINEAR TECHNOLOGY CORP
元件分類: 電源管理
英文描述: Negative Voltage Hot Swap Controllers
中文描述: 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: PLASTIC, MSOP-8
文件頁數(shù): 14/32頁
文件大?。?/td> 327K
代理商: LTC4252-2CMS8
LTC4252-1/LTC4252-2
14
425212f
UV/OV OPERATION
A low input to the UV comparator will reset the chip and
pull the GATE and TIMER pins low. A low-to-high UV
transition will initiate an initial timing sequence if the other
interlock conditions are met. A high-to-low transition in
the UV comparator immediately shuts down the LTC4252,
pulls the MOSFET gate low and resets the latched PWRGD
high.
Overvoltage conditions detected by the OV comparator
will also pull GATE low, thereby shutting down the load.
However, it will not reset the circuit breaker TIMER,
PWRGD flag or shutdown cooling timer. Returning the
supply voltage to an acceptable range restarts the GATE
pin if all the interlock conditions except TIMER are met.
Only during the initial timing cycle does an OV condition
reset the TIMER.
DRAIN
Connecting an external resistor, R
D
, to the dual function
DRAIN pin allows V
OUT
sensing without it being damaged
by large voltage transients. Below 6.15V, negligible pin
leakage allows a DRAIN low comparator to detect V
OUT
less than 2.385V (V
DRNL
). This condition, together with
the GATE low comparator, sets the PWRGD flag.
If V
OUT
> V
DRNCL
(7V), the DRAIN pin is clamped at about
7V and the current flowing in R
D
is given by:
I
V
V
R
DRN
OUT
DRNCL
D
(1)
This current is scaled up 8 times during a circuit breaker
fault and is added to the nominal 230
μ
A TIMER current.
This accelerates the fault TIMER pull-up when the MOSFET’s
drain-source voltage exceeds 7V and effectively shortens
the MOSFET heating duration.
TIMER
The operation of the TIMER pin is somewhat complex as
it handles several key functions. A capacitor C
T
is used at
TIMER to provide timing for the LTC4252. Four different
charging and discharging modes are available at TIMER:
1) A 5.8
μ
A slow charge; initial timing and shutdown
cooling delay.
2) A (230
μ
A + 8 I
DRN
) fast charge; circuit breaker delay.
3) A 5.8
μ
A slow discharge; circuit breaker "cool off" and
shutdown cooling.
4) Low impedance switch; resets the TIMER capacitor
after an initial timing delay, in UVLO, in UV and in OV
during initial timing.
For initial start-up, the 5.8
μ
A pull-up is used. The low
impedance switch is turned off and the 5.8
μ
A current
source is enabled when the interlock conditions are met.
C
T
charges to 4V in a time period given by:
t
V C
4
5 8
.
A
T
=
μ
(2)
When C
T
reaches 4V (V
TMRH
), the low impedance switch
turns on and discharges C
T
. A GATE start-up cycle begins
and both SS and GATE are released.
CIRCUIT BREAKER TIMER OPERATION
If the SENSE pin detects more than a 50mV drop across
R
S
, the TIMER pin charges C
T
with (230
μ
A + 8 I
DRN
). If
C
T
charges to 4V, the GATE pin pulls low and the LTC4252-1
latches off while the LTC4252-2 starts a shutdown cooling
cycle. The LTC4252-1 remains latched off until the UV pin
is momentarily pulsed low or TIMER is momentarily
discharged low by an external switch or V
IN
dips below
UVLO and is then restored. The circuit breaker timeout
period is given by:
t
V C
A
μ +
I
T
DRN
=
4
230
8
(3)
If V
OUT
< 6.15V, an internal PMOS device isolates any
DRAIN pin leakage current, making I
DRN
= 0
μ
A in Equation
(3). If V
OUT
> 7V (V
DRNCL
) during the circuit breaker fault
APPLICATIU
W
U
U
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