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| 型號： | LTC4245CG#TRPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 26/36頁 |
| 文件大?。?/td> | 431K |
| 描述： | IC CNTRLR HOT SWAP 36-SSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | CompactPCI? |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | 3.3V，5V，12V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 36-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 36-SSOP |
| 包裝： | 帶卷 (TR) |
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LTC4245
26
4245fa
Table 2. Sense Resistance Values
SUPPLY
R
SENSE
(1%)
I
TRIP(MIN)
I
TRIP(MAX)
12V
50m?/DIV>
891mA
1.1A
5V
3.5m?/DIV>
6.4A
7.9A
3.3V
2.5m?/DIV>
8.9A
11.1A
12V
100m?/DIV>
396mA
606mA
If necessary, two resistors with the same tolerance can
be connected in parallel to yield the 3.5m?and 2.5m?
values.
2. Select the SS capacitor for limiting the rate of rise of
inrush current. Equations 1 and 2 lead to the following
design equation:
C
G I
R
dI dt
SS MIN
SS SS MAX
SENSE MIN
MA
( )
( )
( )
(
"
"( / )
e
XX)
(6)
Applying Equation 6 to the 12V supply, with G
SS
of 46mV/V,
I
SS(MAX)
of 24糀, R
SENSE(MIN)
of 49.5m? and (dI/dt)
(MAX)
of 150mA/ms yields a C
SS(MIN)
greater than 149nF. This
capacitance value satis es the dI/dt requirements of the
other supplies too. Hence, a 220nF (?0%) capacitor is
chosen for C
SS
.
3. To determine the TIMER capacitance, the time required
to completely power-up all supply outputs simultaneously
needs to be calculated. There are three parts to this time:
time for the internal current limit to cross zero (t
1
), time
for the gate to slew to the MOSFET threshold voltage (t
2
)
and the time for the current ow to charge up the load
capacitors (t
3
) (see Figure 17).
t
1
: The time for the internal current limit to rise above
zero is simply:
t
I
dI dt
FBL MIN
MIN
1
4
= "
( / )
( )
( )
(7)
t
2
: The maximum time for the gate of the external MOSFET to
rise to the threshold voltage depends on I
GATE(UP)(MIN)
and
the gate charge required to turn on the external MOSFET.
A typical value for this time is 1ms. This can be veri ed
after the MOSFETs are selected. Since the current limit
ramp is almost stopped while any MOSFET is turning on,
t
2
is 4 times 1ms or 4ms, since in the worst case none of
the four MOSFET turn-ons overlaps in time.
t
3
: Under simultaneous power-up each output voltage af-
fects the inrush current pro le. To simplify calculations, the
inrush current pro le shown in Figure 17 is chosen. All the
current is assumed to charge the load capacitor, i.e., there
is no load current. There are four parts to t
3
as shown.
Equations 8 to 11 are used to determine t
31
to t
34
:
t
I
dI dt
FBL MIN
MIN
31
=
( )
( )
( / )
(8)
t
C V
I
t
L FB
FBL MIN
32
31
0 5
=
"
. "
( )
(9)
t
I
I
dI dt
C
FBH MIN FBL MIN
MIN
L
33
2
=min
( / )
,
"
( )
( )
( )
""(
)
( / )
( )
V
V
dI dt
t
t
OUT FB
MIN
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
2
31
31
煙
?/DIV>
?/DIV>
?/DIV>
(10)
t
C V
V
t
I
I
L
OUT FB
FBL MIN
34
33
0
0 5
=
+
max
,
"(
) . "
"(
( )
FFBH MIN
FBH MIN
I
( )
( )
)
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
(11)
APPLICATIO S I FOR ATIO
U
U
U
t
1
t
31
V
GATE
= 0
V
GATE
= V
TH
I
NEG
0
I
FBL
I
FBH
V
OUT
= V
FB
V
OUT
= V
IN
(SMALL C
L
)
V
OUT
= V
IN
(LARGE C
L
)
t
32
t
33
t
33
t
34
OR
t
2
4245 F17
INTERNAL CURRENT LIMIT
INRUSH CURRENT FOR LARGER C
L
INRUSH CURRENT FOR SMALLER C
L
Figure 17. Inrush Current Pro le for Design Example
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