參數(shù)資料
型號(hào)： LTC4222CG#PBF
廠商： Linear Technology
文件頁(yè)數(shù)： 18/32頁(yè)
文件大?。?/td> 339K
描述： IC CTRLR DUAL HOT SWAP 36-SSOP
標(biāo)準(zhǔn)包裝： 37
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 2.9 V ~ 29 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 36-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 36-SSOP
包裝： 管件
LTC4222
18
4222fb
APPLICATIONS INFORMATION
Configuring the GPIO Pins
Table 3 describes the possible states of the GPIO pins using
the CONTROL registers bits 6 and 7. At power-up, the default
state is for a GPIO pin to go high impedance when power is
good (FB pin greater than 1.235V). Other applications for a
GPIO pin are to pull down when power is good, a general
purpose output and a general purpose input.
A simple application of the GPIO pin in the power good
configuration is to connect it to the UV pin of the other
channel with the CONFIG pin high. This will result in the
second channel being turned on after the first channel has
started up and signaled power good.
Current Limit Stability
For many applications the LTC4222 current limit will be
stable without additional components. However there are
certain conditions where additional components may be
needed to improve stability. The dominant pole of the cur-
rent limit circuit is set by the capacitance and resistance at
the gate of the external MOSFET , and larger gate capaci-
tance makes the current limit loop more stable. Usually
a total of 8nF gate to source capacitance is sufficient for
stability and is typically provided by inherent MOSFET C
GS
,
however the stability of the loop is degraded by increasing
R
SENSE
 or by reducing the size of the resistor on a gate RC
network if one is used, which may require additional gate
to source capacitance. Board level short-circuit testing
is highly recommended as board layout can also affect
transient performance, for stability testing the worst-case
condition for current limit stability occurs when the output
is shorted to ground after a normal start-up.
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping
at power-up or during current limiting. The first type of
oscillation occurs at high frequencies, typically above
1MHz. This high frequency oscillation is easily damped
with R5 as shown in Figure 1. In some applications, one
may find that R5 helps in short-circuit transient recovery
as well. However, too large of an R5 value will slow down
the turn-off time. The recommended R5 range is between
5?and 500?
The second type of source follower oscillation occurs at
frequencies between 200kHz and 800kHz due to the load
capacitance being between 0.2礔 and 9礔 , the presence
of R5 resistance, the absence of a drain bypass capacitor,
a combination of bus wiring inductance and bus supply
output impedance. To prevent this second type of oscillation
avoid load capacitance below 10礔 , alternately connect an
external capacitor from the MOSFET gate to ground with
a value greater than 1.5nF .
Supply Transients
The LTC4222 is designed to ride through supply transients
caused by load steps. If there is a shorted load and the
parasitic inductance back to the supply is greater than
0.5礖, there is a chance that the supply collapses before
the active current limit circuit brings down the GATE pin.
If this occurs, the undervoltage monitors pull the corre-
sponding GATE pin low. The undervoltage lockout circuit
has a 2祍 filter time after V
DD
 drops below 2.35V . The UV
pin reacts in 2祍 to shut the GATE off, but it is recom-
mended to add a filter capacitor, C
F
, to prevent unwanted
shutdown caused by a transient. Eventually either the UV
pin or undervoltage lockout responds to bring the current
under control before the supply completely collapses.
Supply Transient Protection
The LTC4222 is safe from damage with supply voltages up
to 35V . However, spikes above 35V may damage the part.
During a short-circuit condition, large changes in current
fowing through power supply traces may cause induc-
tive voltage spikes which exceed 35V . To minimize such
spikes, the power trace inductance should be minimized
by using wider traces or heavier trace plating. Also, a
snubber circuit dampens inductive voltage spikes. Build
a snubber by using a 100?resistor in series with a 0.1礔
capacitor between V
DD
 and GND. A surge suppressor, Z1
in Figure 1, at the input can also prevent damage from
voltage surges.
Design Example
As a design example, take the following specifications for
channel 1: V
IN
 = 12V , I
MAX
 = 5A, I
INRUSH
 = 1A, dI/dt
INRUSH
 
= 10A/ms, C
L
 = 330礔 , V
UV(RISING)
 = 10.75V , V
OV(FALLING)
 
= 14.0V , V
PWRGD(UP)
 = 11.6V , and I
2
C ADDRESS = 1000111.
This completed design is shown in Figure 1.
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