LTC4222
11
4222fb
OPERATION
The LTC4222 is designed to turn two supply voltages
on and off in a controlled manner, allowing boards to be
safely inserted or removed from a live backplane. During
normal operation, the charge pump and gate drivers turn
on external N-channel MOSFET gates to pass power to
the loads. The gate driver circuits use a charge pump that
derives its power from the V
DD1
or V
DD2
pin, whichever is
higher. Also included in the gate driver circuits are internal
6.5V GATE-to-SOURCE clamps to protect the oxide of
logic-level MOSFETs. During start-up the inrush currents
are tightly controlled by using current limit foldback, soft-
start dI/dt limiting and output dI/dt limiting. The LTC4222
is capable of controlling both channels independently, or
coupling control signals so that both channels start up
and turn off together.
The current sense (CS) amplifiers monitor the load cur-
rents using the difference between the SENSE
+
(V
DD
for
QFN) and SENSE
pin voltages. A CS amplifier limits the
current in the load by pulling back on the GATE-to-SOURCE
voltage in an active control loop when the sense voltage
exceeds the commanded value. The CS amplifiers require
20礎(chǔ) input bias current from both the SENSE
+
and the
SENSE
pins.
A short circuit on an output to ground results in excessive
power dissipation during active current limiting. To limit this
power, the corresponding CS amplifier regulates the voltage
between the SENSE
+
and SENSE
pins at 150mV .
If an overcurrent condition persists, the internal circuit
breaker (CB) registers a fault when the sense voltage
exceeds 50mV for more than 20祍. This indicates to
the logic that it is time to turn off the GATE to prevent
overheating. At this point the TIMER capacitor starts to
discharge with the 2礎(chǔ) current source until the voltage
drops below 0.2V (comparator TM1) which tells the logic
that the pass transistor has cooled and it is safe to turn
on again if overcurrent auto-retry is enabled. If the TIMER
pin is tied to INTV
CC
, the cool-down time defaults to
5 seconds using an internal system timer.
The output voltages are monitored using the FB resistive
divider and the power good (PG) comparators to determine
when output voltages are acceptable for the loads. The
power good conditions are signaled by the GPIO1 and
GPIO2 pins using open-drain pull-down transistors. The
GPIO pins may also be independently configured to signal
power bad, or as general purpose inputs (GP comparators),
or general purpose open-drain outputs.
The Functional Diagram shows the monitoring blocks of
the LTC4222. The group of comparators on the left side
includes the undervoltage (UV), overvoltage (OV), reset
(RST), enable (EN) and on (ON) comparators for chan-
nel 1 or 2. These comparators determine if the external
conditions are valid prior to turning on their correspond-
ing GATE. The two undervoltage lockout circuits, UVLO1
and UVLO2, validate the input supplies and the internally
generated 3.3V supply, INTV
CC
. UVLO2 also generates
the power-up initialization to the logic circuits as INTV
CC
crosses this rising threshold.
The CONFIG pin is used to select the desired start-up
behavior of the LTC4222. When the CONFIG pin is low,
both channels will start up and turn off simultaneously
and a fault on either channel will result in both channels
turning off, or prevent both channels from starting up.
t
SU, DAT
t
SU, STO
t
SU, STA
t
BUF
t
HD, STA
t
SP
t
SP
t
HD, DATO,
t
HD, DATI
t
HD, STA
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
4222 TD01
SDAI/SDAO
SCL
TIMING DIAGRAM