參數(shù)資料
型號： LTC4221IGN#TRPBF
廠商： Linear Technology
文件頁數(shù)： 20/28頁
文件大小： 272K
描述： IC CTRLR HOTSWAP DUAL 16SSOP
標準包裝： 2,500
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無
電源電壓： 1 V ~ 13.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 16-SSOP
包裝： 帶卷 (TR)
20
LTC4221
4221fa
Timer Function
The TIMER pin controls the initial cycle and the channel
start-up cycles with an external capacitor, C
TIMER
. There
are two comparator thresholds: V
TMR(H)
 (1.234V) and
V
TMR(L)
 (0.4V). In addition, the pin has a 1.9糀 pull-up
current, a 20糀 pull-up current and a N-channel MOSFET
pull-down.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supplies at time
point 1 of Figure 13. The LTC4221 is in reset mode as the
ON1 pin is low. Both GATE pins and the TIMER pin are
pulled low. At time point 2, the short pin makes contact and
both ON pins are pulled high. At this instant, a start-up
check requires that both supply voltages be above UVLO,
at least one ON pin be above 0.851V, both GATE pins
< 0.4V and TIMER < 0.4V. When these four conditions are
fulfilled, the initial cycle begins and the TIMER pin is pulled
high with 1.9糀. At time point 3, the TIMER reaches
V
TMR(H)
  and is pulled down below V
TMR(L)
  by the N-
channel MOSFET pull-down, ending the initial cycle at time
point 4. The initial cycle delay is:
t
V
C
A
INITIAL
TIMER
=
?/DIV>
1 234
1 9
.
"
.
(9)
At time point 4, the LTC4221 checks whether the FILTER
pin is <1.24V and FAULT is > 0.851V. If both conditions are
met, a channel start-up cycle commences.
Start-Up Cycle Without Current Limit
During a channel start-up cycle, the TIMER pin ramps up
with a 20糀 internal pull-up so the start-up cycle delay is:
t
V
V
C
A
STARTUP
TIMER
=
(
)
?/DIV>
1 234    0 4
20
.
  .
"
(10)
At the beginning of the start-up timing cycle (time point 4),
the LTC4221s electronic circuit breaker is armed and each
channel has an internal 9.5糀 current source working with
an internal charge pump to provide the gate drive to its
external pass transistor. At time point 5, GATE1 reaches
the external pass transistor threshold and V
OUT1
 starts to
follow the GATE1 ramp-up. If the inrush current is below
current limit, GATE1 ramps at a constant rate of:
?/DIV>
?/DIV>
=
V
T
I
C
GATE
GATE
GATE
(11)
where C
GATE
 is the total capacitance at the GATE1 pin. The
inrush current through R
SENSE1
 can be divided into two
components; I
CLOAD
  due to the total load capacitance
C
LOAD
 and I
LOAD
 due to the noncapacitive load elements.
The load bypass capacitance typically dominates C
LOAD
.
For a successful channel start-up without current limit,
I
INRUSH
 < active current limit. Due to the voltage follower
configuration, the V
OUT1
 ramp rate approximately tracks
V
GATE1
. The inrush current during a start-up cycle without
current limit is :
I
C
V
T
I
I
C
V
T
I
I
C
I
C
I
INRUSH
LOAD
OUT
LOAD
INRUSH
LOAD
GATE
LOAD
INRUSH
LOAD
GATE
GATE
LOAD
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
+
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
+
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
+
"
"
"
(12)
At time point 6, V
OUT1
 is approximately V
CC1
 but GATE1
ramp-up continues until it reaches a maximum voltage.
This maximum voltage is determined either by the charge
pump or the internal clamp.
APPLICATIO S I FOR ATIO
U
U
U
1.234V
V
CCn
V
OUT1
ONn
TIMER
GATE1
RESET
STATE
INITIAL
TIMING
CHANNEL 1
START-UP
NORMAL
20糀
9.5糀
0.4V
V
TH
DISCHARGE
BY LOAD
4221 F13
0.851V
0.4V
1 2
3 4 5
6
7
1.9糀
Figure 13. Channel 1 Start-Up Without Current Limit
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