參數(shù)資料
型號： LTC4214-1IMS#TRPBF
廠商： Linear Technology
文件頁數(shù)： 19/32頁
文件大?。?/td> 277K
描述： IC CTRLR HOTSWAP NEGVOLT 10MSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 熱交換控制器
應(yīng)用： 通用
內(nèi)部開關(guān)： 無
電源電壓： 6 V ~ 16 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-TFSOP，10-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 10-MSOP
包裝： 帶卷 (TR)
LTC4214-1/LTC4214-2
19
421412f
tween the compensation capacitor C
C
 and the MOSFETs
C
ISS
. The line in Figure 6 is used to select a starting value
for C
C
 based upon the MOSFETs C
ISS
 specification. Opti-
mized values for C
C
  are shown for several popular
MOSFETs. Differences in the optimized value of C
C
 versus
the starting value are small. Nevertheless, compensation
values should be verified by board level short-circuit
testing.
As seen in Figure 5 previously, at the onset of a short-
circuit event, the input supply voltage can ring dramati-
cally owing to series inductance. If this voltage avalanches
the MOSFET, current continues to flow through the MOSFET
to the output. The analog current limit loop cannot control
this current flow and therefore the loop undershoots. This
effect cannot be eliminated by frequency compensation. A
zener diode is required to clamp the input supply voltage
and prevent MOSFET avalanche.
SENSE RESISTOR CONSIDERATIONS
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4214s
V
EE
  and SENSE pins are strongly recommended. The
drawing in Figure 7 illustrates the correct way of making
connections between the LTC4214 and the sense resistor.
PCB layout should be balanced and symmetrical to mini-
mize wiring errors. In addition, the PCB layout for the
sense resistor should include good thermal management
techniques for optimal sense resistor power dissipation.
TIMING WAVEFORMS
System Power-Up
Figure 8 details the timing waveforms for a typical power-
up sequence in the case where a board is already installed
in the backplane and system power is applied abruptly. At
time point 1, the supply ramps up, together with UV/OV,
V
IN
, V
OUT
, DRAIN and PWRGD. At time point 2, V
IN
exceeds V
LKO
 and the internal logic checks for UV > V
UVHI
,
OV < V
OVHI
, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 " V
OS
and TIMER < V
TMRL
. If all conditions are met, an initial
timing cycle starts and the TIMER capacitor is charged by
a 5礎(chǔ) current source pull-up. At time point 3, TIMER
reaches the V
TMRH
 threshold and the initial timing cycle
terminates. The TIMER capacitor is quickly discharged. At
time point 4, the V
TMRL
 threshold is reached and the
conditions of GATE < V
GATEL
, SENSE < V
CB
and
SS < 20 " V
OS
 must be satisfied before a GATE ramp-up
cycle begins. SS ramps up as dictated by R
SS
 " C
SS
 (as in
Equation 6); GATE is held low by the analog current limit
(ACL) amplifier until SS crosses 20 " V
OS
. Upon releasing
GATE, 50礎(chǔ) sources into the external MOSFET gate and
compensation network. When the GATE voltage reaches
the MOSFETs threshold, current begins flowing into the
load capacitor at time point 5. At time point 6, load current
reaches the SS control level and the analog current limit
loop activates. Between time points 6 and 8, the GATE
voltage is servoed, the SENSE voltage is regulated at
V
ACL
(t) (Equation 7) and soft-start limits the slew rate of
APPLICATIO  S I FOR  ATIO
U
U
U
W
CURRENT FLOW
FROM LOAD
CURRENT FLOW
TO 12V BACKPLANE
SENSE RESISTOR
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
TO
SENSE
TO
V
EE
4214 F07
Figure 7. Making PCB Connections to the Sense Resistor
Figure 6. Recommended Compensation
Capacitor C
C
 vs MOSFET C
ISS
MOSFET, C
ISS
 (pF)
0   1000
0
10
25
2000
4000  5000
4214 F06
5
20
15
3000
6000  7000
"
"
"
"
"
"
IRF7803
Si4412ADY
Si4410DY
Si4876DY
Si4864DY
IRF7413
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