參數(shù)資料
型號: LTC4214-1IMS#TRPBF
廠商: Linear Technology
文件頁數(shù): 11/32頁
文件大?。?/td> 277K
描述: IC CTRLR HOTSWAP NEGVOLT 10MSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: 6 V ~ 16 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
LTC4214-1/LTC4214-2
11
421412f
Hot Circuit Insertion
When circuit boards are inserted into a live backplane, the
supply bypass capacitors can draw huge transient cur-
rents from the power bus as they charge. The flow of
current damages the connector pins and glitches the
power bus, causing other boards in the system to reset.
The LTC4214 is designed to turn on a circuit board supply
in a controlled manner, allowing insertion or removal
without glitches or connector damage.
Initial Start-Up
The LTC4214 resides on a removable circuit board and
controls the path between the connector and the load with
an external MOSFET switch (see Figure 1). Both inrush
control and short-circuit protection are provided by the
MOSFET.
A detailed schematic is shown in Figure 2. 12V and
GND receive power through the longest connector pins
and are the first to connect when the board is inserted. The
GATE pin holds the MOSFET off during this time. UV/OV
determines whether or not the MOSFET should be turned
on based upon internal high accuracy thresholds and an
external divider. UV/OV does double duty by also monitor-
ing whether or not the connector is seated. The top of the
divider detects GND by way of a short connector pin that
is the last to mate during the insertion sequence.
Interlock Conditions
A start-up sequence commences once these interlock
conditions are met.
1. The input voltage V
IN
 exceeds 5.1V (UVLO).
2. The voltage at UV > 2.25V.
OPERATIO
Figure 1. Basic LTC4214 Hot Swap Topology
Figure 2. 12V, 2A Hot Swap Controller
3. The voltage at OV < 2.85V.
4. The (SENSE  V
EE
) voltage is < 50mV (V
CB
).
5. The voltage at SS is < 0.2V (20 " V
OS
).
6. The voltage on the TIMER capacitor (C
T
) is < 1.7V (V
TMRL
).
7. The voltage at GATE is < 0.5V (V
GATEL
).
The first three conditions are continuously monitored and
the latter four are checked prior to initial timing or GATE
ramp-up. Upon exiting an OV condition, the TIMER pin
voltage requirement is inhibited. Details are described in
the Applications Information, Timing Waveforms section.
TIMER begins the start-up sequence by sourcing 5礎(chǔ) into
C
T
. If V
IN
, UV or OV falls out of range, the start-up cycle
stops and TIMER discharges C
T
 to less than 1.7V, then
waits until the aforementioned conditions are once again
met. If C
T
 successfully charges to 3V, TIMER pulls low
and both SS and GATE pins are released. GATE sources
50礎(chǔ) (I
GATE
), charging the MOSFET gate and associated
capacitance. The SS voltage ramp limits V
SENSE
 to control
the inrush current. PWRGD pulls active low when GATE is
within 2.8V of V
IN
 and DRAIN is lower than V
DRNL
.
Two modes of operation are possible during the time the
MOSFET is first turning on, depending on the values of
external components, MOSFET characteristics and nomi-
nal design current. One possibility is that the MOSFET will
4214 F01
LTC4214
C
LOAD
PLUG-IN BOARD
BACKPLANE
GND
12V
LONG
LONG
+
LOAD
4214 F02
GND
12V
GND
V
OUT
EN
UV
OV
PWRGD
TIMER
V
EE
V
IN
SENSE    GATE
SS
DRAIN
LTC4214-1
R1
121k
1%
R2
32.4k
1%
R
D
475k
C
T
47nF
Z1: SMAJ15A
C
SS
22nF
C
C
10nF
R
S
0.025&
Q1
IRF7413
R
C
10&
R4
10k
C1
1nF
C
IN
0.1礔
1
2
9
8
10
3
7
6
4
5
Z1
C
X
100nF
R
X
10&
R
IN
470&
R3
10k
C
LOAD
100礔
TYP
LONG
LONG
SHORT
+
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