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參數(shù)資料
| 型號(hào)： | LTC2284UP |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual 14-Bit, 105Msps Low Power 3V ADC |
| 中文描述： | 雙14位，105Msps ADC的低功耗3V的 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 687K |
| 代理商： | LTC2284UP |
LTC2284
2284fa
8
PIU
A
INA+
(Pin 1):
Channel A Positive Differential Analog
Input.
A
INA–
(Pin 2):
Channel A Negative Differential Analog
Input.
REFHA (Pins 3, 4):
Channel A High Reference. Short
together and bypass to Pins 5, 6 with a 0.1
μ
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 5, 6 with an additional 2.2
μ
F ceramic chip capacitor
and to ground with a 1
μ
F ceramic chip capacitor.
REFLA (Pins 5, 6):
Channel A Low Reference. Short
together and bypass to Pins 3, 4 with a 0.1
μ
F ceramic chip
capacitor as close to the pin as possible. Also bypass to
Pins 3, 4 with an additional 2.2
μ
F ceramic chip capacitor
and to ground with a 1
μ
F ceramic chip capacitor.
V
DD
(Pins 7, 10, 18, 63):
Analog 3V Supply. Bypass to
GND with 0.1
μ
F ceramic chip capacitors.
CLKA (Pin 8):
Channel A Clock Input. The input sample
starts on the positive edge.
CLKB (Pin 9):
Channel B Clock Input. The input sample
starts on the positive edge.
REFLB (Pins 11, 12):
Channel B Low Reference. Short
together and bypass to Pins 13, 14 with a 0.1
μ
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 13, 14 with an additional 2.2
μ
F ceramic chip ca-
pacitor and to ground with a 1
μ
F ceramic chip capacitor.
REFHB (Pins 13, 14):
Channel B High Reference. Short
together and bypass to Pins 11, 12 with a 0.1
μ
F ceramic
chip capacitor as close to the pin as possible. Also bypass
to Pins 11, 12 with an additional 2.2
μ
F ceramic chip ca-
pacitor and to ground with a 1
μ
F ceramic chip capacitor.
A
INB–
(Pin 15):
Channel B Negative Differential Analog
Input.
A
INB+
(Pin 16):
Channel B Positive Differential Analog
Input.
GND (Pins 17, 64):
ADC Power Ground.
SENSEB (Pin 19):
Channel B Reference Programming Pin.
Connecting SENSEB to V
CMB
selects the internal reference
and a
±
0.5V input range. V
DD
selects the internal reference
and a
±
1V input range. An external reference greater than
0.5V and less than 1V applied to SENSEB selects an input
range of
±
V
SENSEB
.
±
1V is the largest valid input range.
V
CMB
(Pin 20):
Channel B 1.5V Output and Input Common
Mode Bias. Bypass to ground with 2.2
μ
F ceramic chip
capacitor. Do not connect to V
CMA
.
MUX (Pin 21):
Digital Output Multiplexer Control. If MUX
is High, Channel A comes out on DA0-DA13, OFA; Channel B
comes out on DB0-DB13, OFB. If MUX is Low, the output
busses are swapped and Channel A comes out on DB0-
DB13, OFB; Channel B comes out on DA0-DA13, OFA. To
multiplex both channels onto a single output bus, connect
MUX, CLKA and CLKB together. (This is not recommended
at clock frequencies above 80Msps.)
SHDNB (Pin 22):
Channel B Shutdown Mode Selection
Pin. Connecting SHDNB to GND and OEB to GND results
in normal operation with the outputs enabled. Connecting
SHDNB to GND and OEB to V
DD
results in normal opera-
tion with the outputs at high impedance. Connecting
SHDNB to V
DD
and OEB to GND results in nap mode with
the outputs at high impedance. Connecting SHDNB to V
DD
and OEB to V
DD
results in sleep mode with the outputs at
high impedance.
OEB (Pin 23):
Channel B Output Enable Pin. Refer to
SHDNB pin function.
DB0 – DB13 (Pins 24 to 30, 33 to 39):
Channel B Digital
Outputs. DB13 is the MSB.
OGND (Pins 31, 50):
Output Driver Ground.
OV
DD
(Pins 32, 49):
Positive Supply for the Output Driv-
ers. Bypass to ground with 0.1
μ
F ceramic chip capacitor.
OFB (Pin 40):
Channel B Overflow/Underflow Output.
High when an overflow or underflow has occurred.
DA0 – DA13 (Pins 41 to 48, 51 to 56):
Channel A Digital
Outputs. DA13 is the MSB.
OFA (Pin 57):
Channel A Overflow/Underflow Output.
High when an overflow or underflow has occurred.
OEA (Pin 58):
Channel A Output Enable Pin. Refer to
SHDNA pin function.
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