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參數(shù)資料
| 型號： | LTC2284UP |
| 廠商： | Linear Technology Corporation |
| 英文描述： | Dual 14-Bit, 105Msps Low Power 3V ADC |
| 中文描述： | 雙14位，105Msps ADC的低功耗3V的 |
| 文件頁數(shù)： | 5/24頁 |
| 文件大?。?/td> | 687K |
| 代理商： | LTC2284UP |
LTC2284
5
2284fa
SYMBOL
f
s
t
L
PARAMETER
Sampling Frequency
CLK Low Time
CONDITIONS
(Note 9)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
Duty Cycle Stabilizer Off (Note 7)
Duty Cycle Stabilizer On (Note 7)
MIN
1
4.5
3
4.5
3
TYP
MAX
105
500
500
500
500
UNITS
MHz
●
●
●
4.76
4.76
4.76
4.76
0
2.7
2.7
4.3
3.3
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
H
CLK High Time
●
●
t
AP
t
D
t
MD
Sample-and-Hold Aperture Delay
CLK to DATA Delay
MUX to DATA Delay
Data Access Time After OE
↓
BUS Relinquish Time
C
L
= 5pF (Note 7)
C
L
= 5pF (Note 7)
C
L
= 5pF (Note 7)
(Note 7)
●
1.4
1.4
5.4
5.4
10
8.5
●
●
●
Pipeline Latency
Cycles
SYMBOL
V
DD
OV
DD
IV
DD
P
DISS
P
SHDN
P
NAP
PARAMETER
Analog Supply Voltage
Output Supply Voltage
Supply Current
Power Dissipation
Shutdown Power (Each Channel)
Nap Mode Power (Each Channel)
CONDITIONS
(Note 9)
(Note 9)
Both ADCs at f
S(MAX)
Both ADCs at f
S(MAX)
SHDN = H, OE = H, No CLK
SHDN = H, OE = L, No CLK
MIN
2.85
0.5
TYP
3
3
180
540
2
15
MAX
3.4
3.6
210
630
UNITS
●
V
V
●
●
mA
mW
mW
mW
●
POWER REQUIREW
range, otherwise specifications are at T
A
= 25
°
C. (Note 8)
U
The
●
denotes the specifications which apply over the full operating temperature
TIW
range, otherwise specifications are at T
A
= 25
°
C. (Note 4)
The
●
denotes the specifications which apply over the full operating temperature
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2:
All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3:
When these pin voltages are taken below GND or above V
DD
, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V
DD
without latchup.
Note 4:
V
DD
= 3V, f
SAMPLE
= 105MHz, input range = 2V
P-P
with differential
drive, unless otherwise noted.
Note 5:
Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6:
Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and
11 1111 1111 1111.
Note 7:
Guaranteed by design, not subject to test.
Note 8:
V
DD
= 3V, f
SAMPLE
= 105MHz, input range = 1V
P-P
with differential
drive. The supply current and power dissipation are the sum total for both
channels with both channels active.
Note 9:
Recommended operating conditions.
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