參數(shù)資料
型號: LTC2274IUJ#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
封裝: 6 X 6 MM, PLASTIC, QFN-40
文件頁數(shù): 5/40頁
文件大?。?/td> 897K
代理商: LTC2274IUJ#TR
LTC2274
13
2274fb
CORRECTION
LOGIC
8B/10B
ENCODER
SCRAMBLER/
PATTERN
GENERATOR
PLL
20X CLK
VCM
22743 BD
SYNC+
SYNC
PAT1
PAT0
SRR1
SRR0
SCRAM
VDD
OVDD
GND
CMLOUT+
CMLOUT
20
SERIALIZER
CONTROL LOGIC
MSBINV
SHDN
DITH
PGA
CLOCK DRIVER
WITH DUTY CYCLE
CONTROL
2.5V
REFERENCE
ADC
REFERENCE
1x OR 2x
0.5x
REFERENCE
CONTROL
ENC
ENC+
FAM
SENSE
16
+
DITHER SIGNAL
GENERATOR
S/H
AND PGA
AIN
AIN
+
FIRST
STAGE
SECOND
STAGE
THIRD
STAGE
PIPELINED ADC STAGES
FOURTH
STAGE
FIFTH
STAGE
BLOCK DIAGRAM
Figure 1. Functional Block Diagram
SENSE (Pin 38): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal
2.5V bandgap reference. An external reference of 2.5V or
1.25V may be used; both reference values will set a full
scale ADC range of 2.25V (PGA = 0).
VCM (Pin 39): 1.25V Output. Optimum voltage for input
common mode. Must be bypassed to ground with a
minimum of 2.2μF. Ceramic chip capacitors are recom-
mended.
GND (Exposed Pad) (Pin 41): ADC Power Ground. The
Exposed Pad on the bottom of the package needs to be
soldered to ground.
PIN FUNCTIONS
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