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參數(shù)資料
| 型號： | LTC2274IUJ#TR |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40 |
| 封裝： | 6 X 6 MM, PLASTIC, QFN-40 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 897K |
| 代理商： | LTC2274IUJ#TR |
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LTC2274
23
2274fb
APPLICATIONS INFORMATION
SERIALIZED DATA FRAME
Prior to serialization, the ADC data is encoded into the
8B/10B format, which is DC balanced, and run-length
limited. The receiver is required to lock onto the data
and recover the clock with the use of a PLL. The 8B/10B
format requires that the ADC data be broken up into 8-bit
blocks (octets), which is encoded into 10-bit code groups
applying the 8B/10B rules (refer to IEEE Std 802.3-2002
Part 3, for a complete 8B/10B description).
Figure 12 illustrates the generation of one complete 8B/10B
frame. The 8 most signicant bits of the ADC are assigned
to the rst half of the frame, and the remaining 8 bits
to the second half of the frame. Next, the two resulting
octets are optionally scrambled and encoded into their
corresponding 8B/10B code. Finally, the two 10-bit code
groups are serialized and transmitted beginning with Bit
0 of code group 1.
+–
AIN–
AIN+
S/H
AMP
DIGITAL
SUMMATION
8b10b
ENCODER
MULTIBIT DEEP
PSEUDO-RANDOM
NUMBER
GENERATOR
16-BIT
PIPELINED
ADC CORE
PRECISION
DAC
CLOCK/DUTY
CYCLE
CONTROL
ENC
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF
DITH
ENC
ANALOG
INPUT
2274 F11
LTC2274
CMLOUT+
CMLOUT–
SERIALIZER
Figure 11. Functional Equivalent Block Diagram of Internal Dither Circuit
Figure 12. Evolution of One Transmitted Frame (Compare to IEEE Std 802.3-2002 Part 3, Figure 36-3)
BIT
15
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
BIT
9
BIT
10
BIT
11
BIT
12
BIT
13
BIT
14
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HA
B
C
D
E
F
G
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HA
B
C
D
FIRST OCTET
ADC OUTPUT WORD
MSB
LSB
OCTET
ASSIGNMENT
OPTIONAL
SCRAMBLER
8B/10B
ENCODER
E
F
G
BIT
2
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
0
BIT
1
cj
h
g
f
FIRST SCRAMBLED OCTET
8B/10B CODE GROUP 1
BIT 0 OF CODE GROUP 1 IS TRANSMITTED FIRST
i
e
d
ab
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HB
A
C
D
E
F
G
BIT
7
BIT
0
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
HB
A
C
D
SECOND OCTET
E
F
G
BIT
2
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
0
BIT
1
ch
j
g
f
SECOND SCRAMBLED OCTET
8B/10B CODE GROUP 2
i
e
d
ab
ONE FRAME
SERIAL OUT
2274 F12
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