參數(shù)資料
型號: LTC2274IUJ#TR
廠商: LINEAR TECHNOLOGY CORP
元件分類: ADC
英文描述: 1-CH 16-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC40
封裝: 6 X 6 MM, PLASTIC, QFN-40
文件頁數(shù): 19/40頁
文件大?。?/td> 897K
代理商: LTC2274IUJ#TR
LTC2274
26
2274fb
SYNC
REQUEST?
START
IS ISMODE
ENABLED?
NEGATIVE
DISPARITY?
DATA TRANSMISSION
FLOW (SEE FIGURE 18)
TRANSMIT K28.5
AS CODE GROUP 1
WAIT FOR NEXT
FRAME CLOCK
TRANSMIT K28.5
AS CODE GROUP 2
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT D5.6
AS CODE GROUP 2
TRANSMIT K28.5
AS CODE GROUP 1
TRANSMIT D16.2
AS CODE GROUP 2
NO
YES
NO
YES
NO
(DISPARITY NOT OK)
(NEGATIVE DISPARITY)
(DISPARITY IS OK)
(POSITIVE DISPARITY)
(NEGATIVE DISPARITY)
2274 F15
YES
APPLICATIONS INFORMATION
Figure 15. Initial Synchronization Flow Diagram
Scrambling
To avoid spectral interference from the serial data output,
an optional data scrambler is added between the ADC
data and the 8B/10B encoder to randomize the spectrum
of the serial link. The scrambler is enabled by setting the
SCRAM pin to a high logic level. The polynomial used for
the scrambler is 1 + x14 + x15, which is a pseudo-random
pattern repeating itself every 215–1. Figure 16 illustrates
the LTC2274 implementation of this polynomial in parallel
form.
The scrambled data is converted into two valid 8B/10B
code groups, constituting a complete frame. The 8B/10B
code groups are then serialized and transmitted.
The receiver is required to deserialize the data, decode
the code-groups into octets and descramble them back
to the original octets using the self-aligning descrambler
shown in Figure 17. This descrambler is shown in 16-bit
parallel form, which is an efcient implementation of the
(1 + x14 + x15) polynomial, operating at the frame clock
rate (ADC sample rate).
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