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參數(shù)資料
| 型號： | LTC2184IUP#TRPBF |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | ADC |
| 英文描述： | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| 封裝： | 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大?。?/td> | 799K |
| 代理商： | LTC2184IUP#TRPBF |
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LTC2185/LTC2184/LTC2183
24
218543f
applicaTions inForMaTion
Phase Shifting the Output Clock
In Full Rate CMOS mode the data output bits normally
change at the same time as the falling edge of CLKOUT+,
so the rising edge of CLKOUT+ can be used to latch the
output data. In Double Data Rate CMOS and LVDS Modes
the data output bits normally change at the same time as
the falling and rising edges of CLKOUT+. To allow adequate
set-up and hold time when latching the data, the CLKOUT+
signal may need to be phase shifted relative to the data
output bits. Most FPGAs have this feature; this is generally
the best place to adjust the timing.
The LTC2185/LTC2184/LTC2183 can also phase shift the
CLKOUT+/CLKOUT–signalsbyseriallyprogrammingmode
control register A2. The output clock can be shifted by 0°,
45°, 90°, or 135°. To use the phase shifting feature the
Clock Duty Cycle Stabilizer must be turned on. Another
control register bit can invert the polarity of CLKOUT+ and
CLKOUT–, independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 14).
DATA FORMAT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
Table 1. Output Codes vs Input Voltage
AIN+ – AIN–
(2V Range)
OF
D15-D0
(OFFSET BINARY)
D15-D0
(2’s COMPLEMENT)
>1.000000V
+0.999970V
+0.999939V
1
0
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
0
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
<–1.000000V
0
1
0000 0000 0000 0001
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
CLKOUT+
D0-D15, OF
PHASE
SHIFT
0°
45°
90°
135°
180°
225°
270°
315°
CLKINV
0
1
CLKPHASE1
MODE CONTROL BITS
0
1
0
1
CLKPHASE0
0
1
0
1
0
1
0
1
218543 F14
ENC+
Figure 14. Phase Shifting CLKOUT
相關PDF資料 |
PDF描述 |
|---|---|
| LTC2183CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2184IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2185IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2183IUP#PBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
| LTC2184CUP#TRPBF | 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LTC2185 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator |
| LTC2185CUP#PBF | 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 125M SRL/PAR 64-QFN |
| LTC2185CUP#PBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP |
| LTC2185CUP#TRPBF | 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 125M SRL/PAR 64-QFN |
| LTC2185CUP#TRPBF-ES | 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R |
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