參數(shù)資料
型號(hào)： LTC2184IUP#TRPBF
廠商： LINEAR TECHNOLOGY CORP
元件分類： ADC
英文描述： 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
封裝： 9 X 9 MM, LEAD FREE, PLASTIC, MO-220WNJR-5, QFN-64
文件頁數(shù)： 15/36頁
文件大?。?/td> 799K
代理商： LTC2184IUP#TRPBF
LTC2185/LTC2184/LTC2183
22
218543f
50
100
0.1F
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
50
LTC2185
218543 F12
ENC–
ENC+
0.1F
T1
applicaTions inForMaTion
Figure 12. Sinusoidal Encode Drive
ENC+
ENC–
PECL OR
LVDS
CLOCK
0.1F
218543 F13
LTC2185
Figure 13. PECL or LVDS Encode Drive
VDD
LTC2185
218543 F10
ENC–
ENC+
15k
VDD
DIFFERENTIAL
COMPARATOR
30k
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
30k
ENC+
ENC–
218543 F11
0V
1.8V TO 3.3V
LTC2185
CMOS LOGIC
BUFFER
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
through 10k equivalent resistance. The encode inputs
can be taken above VDD (up to 3.6V), and the common
mode range is from 1.1V to 1.6V. In the differential encode
mode, ENC– should stay at least 200mV above ground to
avoid falsely triggering the single ended encode mode.
For good jitter performance ENC+ and ENC– should have
fast rise and fall times.
Thesingle-endedencodemodeshouldbeusedwithCMOS
encode inputs. To select this mode, ENC– is connected
to ground and ENC+ is driven with a square wave encode
input. ENC+ can be taken above VDD (up to 3.6V) so 1.8V
to3.3VCMOSlogiclevelscanbeused.TheENC+threshold
is 0.9V. For good jitter performance ENC+ should have fast
rise and fall times.
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% (±5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (Serial Programming Mode), or by CS (Parallel
Programming Mode).
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken to
makethesamplingclockhavea50%(±5%)dutycycle.The
duty cycle stabilizer should not be used below 5Msps.
DIGITAL OUTPUTS
Digital Output Modes
TheLTC2185/LTC2184/LTC2183canoperateinthreedigital
output modes: full rate CMOS, double data rate CMOS (to
halvethenumberofoutputlines),ordoubledatarateLVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (Serial Programming
相關(guān)PDF資料
PDF描述
LTC2183CUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2184IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2185IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2183IUP#PBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
LTC2184CUP#TRPBF 2-CH 16-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQCC64
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LTC2185 制造商:LINER 制造商全稱:Linear Technology 功能描述:30MHz to 1.4GHz IQ Demodulator
LTC2185CUP#PBF 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP 制造商:Linear Technology 功能描述:IC ADC 16BIT 125M SRL/PAR 64-QFN
LTC2185CUP#PBF-ES 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP
LTC2185CUP#TRPBF 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R 制造商:Linear Technology 功能描述:IC ADC 16BIT 125M SRL/PAR 64-QFN
LTC2185CUP#TRPBF-ES 制造商:Linear Technology 功能描述:ADC Dual 125Msps 16-bit Parallel/Serial (SPI)/LVDS 64-Pin QFN EP T/R
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