參數(shù)資料
型號： LSI53C810A
英文描述： LSI53C810A PCI to SCSI I/O Processor technical manual v2.1 3/01
中文描述： LSI53C810A的PCI到SCSI I / O處理器技術(shù)手冊2.1 3 / 01
文件頁數(shù)： 83/166頁
文件大?。?/td> 1330K
代理商： LSI53C810A
SAF-TE Module
3-35
Initiator Operations during a Code Load
Firmware uploads require that the Initiator issue a sequence of Mode 4
Write Buffer commands. As specified in the SAF-TE and SCSI-2
specifications, Write Buffer command CDBs use bytes 3–5 for the write
address and bytes 6–8 for the transfer length, where the Most Significant
Byte (MSB) is presented first.
The SAF-TE firmware requires that the MSB of the transfer length, that
is, Byte 6, will always be 0. If this byte is not zero, the CDB will result in
a check condition indicating an invalid field in the CDB.
Table 3.11
background_code_load operation
cl_byte_count value
background_code_load
operation
CLBC_UPDATE_STRUCTURE
(0)
Set up TWS bus, set bytes 0 and 1 of
code_buffer
, call
tws_memory_write
to
update the EEPROM. If write is
successful, set
cl_status
to
CLS_SUCCESS
; else set
cl_status
to
CLS_FAILURE_NVM
.
CLBC_REBOOT (1)
Turn off interrupts, set timer, and delay
until a soft reset occurs.
Any value > 1
Validate write address. If invalid, set
cl_status
to
CLS_FAILURE_ADDRESS
.
Validate image checksum. If invalid, set
cl_status
to
CLS_FAILURE_CHECKSUM
.
Decrement the byte count pointer
because any data transferred as part of a
firmware update must have a checksum
as the last byte. This byte is not part of
the firmware.
Update
cl_addr
with the starting address
of the inactive image number.
Set up TWS bus and call
tws_memory_write.
If write is successful,
set
cl_status
to
CLS_SUCCESS
;
else set
cl_status
to
CLS_FAILURE_NVM
.
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參數(shù)描述
LSI53C810AE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C810AE single-chip PCI-SCSI controller
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LSI53C825A-160QFP 制造商:LSI Corporation 功能描述:
LSI53C825AE 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LSI53C825AE single-chip PCI-SCSI controller
LSI53C825AJ-160QFP 制造商:LSI Corporation 功能描述:
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